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01:08:06
Mastering Verilog in 1 Hour: A Complete Guide to Key Concepts
31:42
UVM Testbench code for 8:1 Multiplexer | UVM for Design verification fresher
07:56
The Rise of MOSFET | VLSI Stories
25:22
UVM verification Code vs System Verilog verification Code | Complete Code Comparison
53:17
Complete UVM Verification Project for Beginner | Edapayground Link
08:06
FREE VLSI Courses in Jan Feb 2025 | Get Certified in VLSI Design, DFT, Physical Design, Testing
05:24
Complete Road Map for VLSI Jobs from Basics to Advanced in 2025 for Students and Freshers
23:51
UVM code for FIFO Verification | Part 2 | Test cases, Monitor, Scoreboard
30:36
UVM Testbench for FIFO Verification | Part 1 | UVM code for Fresher
19:57
UVM Testbench code and execution flow of Phases
11:35
AMBA Protocols APB, AHB, AXI, ACE, CHI | Overview, Applications, Limitations
32:01
Synchronous FIFO Design code and Verification Testbench | Verilog code | First in First out
03:04
Semiconductor Revolution in India | VLSI Future in India
18:49
APB Protocol Testbench Code | Verification of APB Memory | Part 3
02:59
Qualcomm Hiring Freshers 2025 | CS, EC, EE or related branch BE/ MTech
13:07
APB Protocol Design and Verification | APB Memory Design | Part 2
08:22
5 FREE Courses for VLSI Fresher | 100% FREE | July 2024 #vlsitraining
01:37
Micron Hiring Freshers for VLSI Jobs | Diploma, BE, MTech
09:11
System verilog Constructor new( ) function | Why it is used? Advantages
14:38
Exploring The Top Vlsi Companies And Ecosystem Trends! #vlsi
12:56
Flip Flops in Digital Electronics | S R Flipflop, D Flip flop , J K flipflop, T Flip FLop
19:14
APB Protocol Read Write Transactions | with & without wait states | AMBA #APB PART1
01:01
Roadmap to Design Verification Engineer Role | VLSI Jobs
12:24
5 Important things to know about VLSI Design Verification | Road map to DV
29:07
System Verilog Testbench code for Full Adder | VLSI Design Verification Fresher #systemverilog
01:01
FREE Siemens Course on VLSI for Students FREE of Cost! #vlsitraining #ams #vlsi #jobs
06:19
INDIA needs you | How to start VLSI Career | VLSI opportunities for Freshers
02:03
5 Easy Steps to become a VLSI Engineer as Fresher
39:08
UVM Testbench code for Fresher / Beginners | UVM for Design verification fresher
08:54
verilog Case statements and example | Casex Casez
08:44
Full Adder using Verilog Data Flow and Structural modeling.
03:55
half adder in verilog all modeling styles
06:03
fork join, join any, join none in system Verilog
11:51
System Verilog Interview Questions| Design Verification Interview Questions
16:02
UVM testbench example code from scratch | Run phase | Part 4
08:06
UVM Testbench code from Scratch for D flipflop | Part 3 | Connect Phase
10:24
Explore Vlsi Jobs and Roles | VLSI Job Domains | How to choose #vlsi
18:06
Verilog Basics With Introductory Video | Part 2
12:08
UVM Testbench code | Complete uvm Testbench for D Flipflop | PART 2 | UVM Example code
21:33
UVM Testbench code | Complete uvm Testbench for D Flipflop | PART 1 | UVM code with example
06:01
Synchronous Reset Asynchronous Reset in Sequential design with verilog code
09:06
blocking and nonblocking in verilog | swap registers using Blocking Non Blocking #verilog
09:45
UVM Report Macros | UVM Tutorial #1
04:57
Introduction to UVM | Design Verification using UVM | UVM Basics #uvm
05:41
Introduction to System Verilog Playlist | Design Verification using System Verilog
04:43
Verilog Basics With Introductory Video | Part 1 | Introduction to Verilog