30:02

#5 Verilog Interview Questions and Answers || verilog Q & A series

33:44

#4 Verilog Interview Questions and Answers || verilog Q & A series

10:34

#3 Verilog Interview Questions and Answers || verilog Q & A series

10:47

#2 Verilog Interview Questions and Answers || Verilog Interview Q &A series

16:03

#1 Verilog Interview Questions and Answers || verilog Interview Q&A series

31:37

RTL based Memory Verification || How industry standard Testbench is written for Verification

32:29

RTL based Verification || functional verification ||Types of testbench ||Stimulus,driver,DUT,monitor

33:06

VLSI Design Flow || specification to GDS2 ||Both FPGA and ASIC design flow || what exactly is GDSII

16:40

#38-1 Difference between REG and WIRE in verilog, their physical meaning,How to choose REG and WIRE

03:13

FPGA based project || RUBIC cube solver || Project link provided

06:44

Square wave extension digital logic diagram with explanation || interview question

20:59

#19-1 Blocking and Non Blocking assignment in a always Block || very important concept

39:12

#41 Hardware implementation of FSM ||understand FSM diagram and how to draw digital circuit from FSM

06:52

#18-1 How multiple #0 delays are executed in verilog || zero delay control in verilog

07:32

#3-1 Number representation in verilog || Number format in verilog

05:27

#2-1 Replicate & Concatenation operator in verilog|| Most used operator in verilog ||very important

52:24

SET UP & HOLD TIME ||it's physical meaning|| it's importance||How it's related to CMOS, Capacitor

15:39

Edge Detection Logic||Explanation with digital filter & verilog code || Different clock in same code

04:06

#4-1 STRING Data type in verilog || Data type in verilog

09:47

#12-1 Use of always@(*) in verilog || combinatioal logic design in verilog || very important concept

07:26

#10-1 Difference between GATE level and STRUCTURAL Modelling in verilog || interview question

11:32

#31-1 forever vs always vs initial in verilog ||forever in verilog||always, initial ||very important

30:14

Difference between VERIFICATION, TESTING & VALIDATION in VLSI Design

43:31

VLSI Project || DAC( Digital to Analog Converter) interfacing with FPGA using SPI || SPARTAN 3E

42:22

LCD Interfacing with FPGA ||Working verilog code||Working principle is same for Microcontroller also

49:01

(Part -3) Digital logic SYNTHESIS || why synthesis || Synthesis flow || Synthesis interview question

01:08:12

( Part -2 ) RTL Coding Guidelines || What is RTL || RTL Code = verilog code + RTL coding guidelines

01:08:20

VLSI Project || RF based WIRELESS data transmission between two FPGA ||SPI || NRF24L01||Verilog Code

25:23

( Part -1 ) SPEC in VLSI Design|| Datasheet for chip designing || Frontend Design flow

01:35:43

I2C protocol with Verilog code || Onboard I2C controlled EEPROM Interfacing with FPGA

26:14

VGA Interfacing with FPGA || explanation with working Verilog code

46:11

What is an IP in VLSI Design || Types of IP(soft,Hard,Firm IP) || How IP Licensing works

20:08

VLSI INTERVIEW QUESTIONS || RTL/ Digital Logic Design questions || Verilog & Digital logic questions

20:40

ASIC in VLSI Design || Types of ASIC

34:03

I2C Protocol Basics || Why I2C lines are OPEN DRAIN

23:36

File Reading and Writing in Verilog || explanation with working Verilog code || very important

01:11:39

VLSI Project || ADC(Analog to Digital Converter) & SENSOR interfacing with FPGA using SPI

38:40

Serial Peripheral Interface || SPI PROTOCOL || explanation with Verilog code and Testbench

24:31

#40 Finite state machine(FSM) | Moore state machine |sequential logic design | Mealy vs Moore

36:48

#39 Finite state machine(FSM) | Mealy state machine |sequential logic design |writing FSM in verilog

44:19

#38 Wire vs Reg | when to use wire and reg, confused ? must watch | All the rules for WIRE and REG

15:37

#37 (MISTAKE-Read Description) FUNCTION in verilog || It's Uses & features || explanation with code

15:09

#36 (MISTAKE-Read Description) TASK in verilog || Use and features of TASK |l explanation with code

08:46

#35 Named block in verilog || verilog block statements

08:11

#34 " fork and join " in verilog || parallel blocks || complete explanation with verilog code

08:56

#33 "generate" in verilog | generate block | generate loop | generate case | explanation with code

12:01

#31 " forever " in verilog || How to generate signal with different duty cycles using "forever"

08:16

#32 " repeat " in verilog || realtime example || Synthesizable " repeat " statement

23:38

Why M.Tech VLSI is so demanding || Why GATE Rankers prefer VLSI Design || The Reality || The Truth

08:09

#30 "while" loop in verilog || Hardware meaning of while loop || while loop synthesizable or not

11:56

#29 "for" loop in verilog || Hardware meaning of "for loop" || synthesizable "for" loop in verilog

12:20

#28 casex vs casez in verilog | Explained with verilog code

12:23

#27 "case" statement in verilog | if-else vs CASE || when to use if-else and case in verilog

08:25

#26 if-else in verilog |conditional statement in verilog |Hardware implementation of if-else verilog

12:13

#25 Difference between ALWAYS and INITIAL Block in verilog || VLSI interview question

25:58

#24 INITIAL block in verilog | use of INITIAL procedural block in verilog

11:17

#23 Multiple ALWAYS block in verilog | procedural blocks in verilog | Multi driver error in verilog

24:21

#22 How to write TESTBENCH in verilog || use of $monitor, $display,$Stop,$finish in verilog

15:08

#21 Why delays are not synthesizsble in verilog or HDL | VLSI interview question

25:49

#20 Inter and intra assignment delay | gate delay,wire delay,inertia and transport delay in verilog