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Analog Layout Laboratory @UCgZEUbcl6Ma6r-Fi7SA6c9g@youtube.com

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This Channel Shares Rare and Useful Information About Analog


13:16
Photomask / Mask Set Layer on 28nm
25:55
TSMC 16nm VS 28nm Layout Comparison
10:09
Basic Photomask / Mask Set Layer on 28nm
17:18
Introduction to Semiconductor Manufacturing Technology (Part-1)
08:48
DNW Diode Extraction Cross-sectional View (Part-5)
10:35
DNW Diode Extraction - Layout Mistakes (Part-4)
10:32
DNW Diode Extraction - Schematic Update (Part-3)
16:05
DNW Diode Extraction - LVS Clearance (Part-2)
17:06
DNW Diode Extraction - Addition of Manual Guard Ring (Part-1)
18:40
Antenna Problem in MIM Capacitor
14:47
How to use PSUB2 layer In TSMC Foundry PDK
20:48
How to Install GPDK – 45nm PDK (Part - 2)
04:11
How to Download GPDK – 45nm PDK (Part - 1)
21:30
IC555 - Chip Die Layout
23:26
ESP8266 - Chip Die Layout
25:37
Ring Oscillator Design & Serpentine Routing (Part-2)
20:33
Ring Oscillator Design & Layout (Part-1)
26:51
High/Low Voltage LDMOS Layout Design - Part 2
16:46
High/Low Voltage LDMOS Layout Understanding - Part 1
26:50
Interdigitation vs Common Centroid Matching
33:35
FinFet DRM, Design Process
12:27
3D view of CMOS - Inverter
06:23
How to Install Linux Virtual Machine
10:53
LDO – Temporary Floor Plan & Power Plan (Part - VIII)
34:26
LDO - Part VII
26:36
LDO - Part VI
16:45
LDO – Error Amp / Pass Transistor Routing - (Part - V)
31:06
LDO - Pmos Routing (Part - IV)
10:10
Mosfet inverter -5T,6T Devices
12:25
Mosfet Types 3T,4T,5T,6T Devices - [ Part I ]
07:29
LDO - Current Calculation (Part - III)
10:36
LDO - Low Dropout Regulator (Part - II)
19:38
FinFet - Design challenges - Corner Effect
00:22
Tech Tale - channel introduction
16:14
DNW - Deep Nwell (Part-3)
08:28
DNW - Deep Nwell (Part-2)
25:43
DNW - Deep Nwell (Part-1)
14:09
Cloning in layout
11:07
EM Calculation & Current Calculation - Part 2
19:10
EM Calculation & Current Calculation
05:45
Bus Creation
07:08
Binding in Layout
09:57
7nm FINFET Layout
17:26
Unit Cell Concept - Part 2
29:32
Unit Cell Concept - Part 1
24:47
Floor Plan Design - Part 1
10:21
Etching Process - English Version
05:18
Plasma Etching - (part - 1)
32:42
Systematic Mismatch - English Version
13:03
Random Mismatch - English Version
07:57
LDO Vs BGR - English Version
13:45
LDO - Low Dropout Regulator (Part - I)
20:05
BGR – Part 1
14:16
Channel Length Modulation - English Version
21:15
Why we Need Resistor Matching - English Version
15:47
Types of Resistor - English Version
16:24
Standard cell layout - English Version
13:19
Standard cell - English Version
15:12
Body Effect - English Version
20:44
Short Channel Effect - English Version