00:37
3. Number of clock cycles taken when there is no forwarding circuitry
00:55
2. How many stalls are required in lw data dependency for 6 stage pipeline
00:31
1. Determining number of cycles in 6 stage pipeline
04:27
127. Determining Index | Tag | Byte Offset fields in Cache - Activity
07:18
126. Effects of increasing block size on Miss rate
07:15
125. How to find data block in memory and map it to a block in cache.
02:32
124. Example - How to calculate total bits in a Cache
05:01
123. Address subdivision and actual size of Cache in bits
07:20
122. Quick review of Memory Hierarchy and Cache
13:31
116. How to stall a cycle in load data hazards | Hazard Detection Unit
05:58
121. Tag and Valid bits in Cache with example
04:48
120. Basics of Cache and Direct Cache Mapping
06:22
119. Principal of Locality and Memory Hierarchy Levels
03:54
118. Introduction to Memory Hierarchy
12:06
117. Pipeline Hazards Detection and Handling - Activity
07:49
115. Revised MEM forwarding conditions for Double Data Hazards
10:54
114. Double Data Hazards
07:13
113. Forwarding Signals | Activity
02:13
112. Forwarding Path | Activity
12:45
111. Updated forwarding conditions for instructions to not write to registers | forwarding hardware.
13:05
110. Conditions to decide when and from which pipelines register to forward the data from.
06:57
109. Pipeline Control
03:16
108. How pipeline registers help writing the correct register value to memory in SW instructions.
05:50
107. Correct path to define destination register Rd
04:22
106. What are Pipeline Registers and why do we need them?
03:13
105. Which path causes the data and control hazards in pipeline architecture?
08:36
104. Branch Hazards
06:47
103. Solving Data Hazards with Code Reordering
06:27
102. Solving Data Hazards with Forwarding
04:35
101. Solving Data Hazard by Waiting | Stalling | Bubble
05:02
100. Pipeline Data Hazards
03:22
99. Structural Hazards in Pipeline processor
00:55
98. Pipeline Hazards
02:47
97. Speedup in processor pipelines
08:37
96. Pipeline vs Single Cycle Processor
06:37
95. Performance issues in Single cycle processor
03:13
94. What happens when a signal wire is stuck at 0?
23:01
91. Creating a single-cycle processor diagram on white board.
10:52
92. Control Signals for different Instructions
01:54
93. Constructing Processor using puzzle - Activity
00:36
90. Control Signals for different instructions | Activity
19:53
89. RISC V Processor Control Signals
22:26
86. Creating RISC V processor incrementally
03:04
88. Check Your Knowledge
03:48
87. Why do we have separate instruction and data memories in RISC V Processor
19:59
85. Brief Overview of RISC V Single Cycle Processor
13:08
84. Single Cycle RISC V Processor | Understanding Processor's Building Blocks
03:09
83. Multiplication | Activity
07:02
82. Multiplication
04:05
81. Performance | Activity
16:19
80. Performance of Computer II
11:12
79. Performance of Computer I
15:02
78. Inside Register File | How to read or write register
07:30
77. Registers as storage elements
19:02
76. Storage Elements
04:34
75. Discussion about clock signal
06:29
74. Quick overview of Sequential Circuits
04:39
73. Quickly review of Decoder and Multiplexer
07:51
69. Arithmetic and Logic Unit - I
04:57
68. Integer Addition and Overflow
X
About
Tags