18:21

7 9 Combinational ATPG, FAN open source code(*optional)

35:24

18 6 Advanced Topics: Power-aware ATPG

30:51

18 5 Advanced Topics: timing-aware ATPG

20:44

18 4 Advanced Topics: N-detect, cell-aware tests

26:14

18 3 Advanced Topics: IDDQ testing

23:32

18 1 Advanced Topics: Defects

13:25

18 2 Advanced Topics: Defect-based testing, Very Low Voltage testing

38:04

17 2 FunctionTest CheckExp (revised June, 2021)

26:12

2 4 LogicSim EventDriven (new version 2021)

13:15

8 5 Sequential ATPG Conclusion (*optional)

27:46

8 4 Sequential ATPG Simulation (*optional)

25:10

8 3 Sequential ATPG: Backward Time Frame Processing (*optional)

26:16

10 4 Diagnosis EffectCause (*optional)

28:09

15 3 Test Compress Hardware Stimulus (updated 5/10/2020)

23:15

5 5 FaultSim DiffFsim(*optional)

28:46

10 5 Diagnosis, Chain Diagnosis (*optional)

25:18

16 3 MemTest March

23:41

16 2 Memory Test - Classical algorithms

32:25

16 1 MemTest Intro

28:35

4 2 Dominance Fault Collapsing, DFC (*optional)

21:24

11 2 DFT1 ScanConcepts

36:50

13 2 BIST1 LFSR

29:29

13 5 BIST1 CA

26:59

9 3 DelayTest PathTG

21:00

12 3 DFT2 Instruction (New version)

28:09

15 3 TestCompress HardwareStimulus

21:49

7 2 Combinational ATPG (Boolean Difference)

36:29

7 5 Combinational ATPG, PODEM

08:48

7 7 Combinational ATPG, SAT

28:04

3 4 FaultModeling DelayFault

32:11

5 6 FaultSim Alternatives

19:06

3 3 FaultModeling BridgeFault

26:05

2 4 LogicSim EventDriven

12:51

2 3 LogicSim CompliedCode

30:59

1 2 Introduction Types Of Tests

13:17

1 5 ReferenceDedication (*optional)

34:56

17 3 FunctionTest IOV

15:56

17 4 FunctionTest SV (*optional)

29:50

15 4 TestCompress HardwareResponse (*optional)

19:32

17 1 FunctionTest Intro

28:09

15 3 TestCompress HardwareStimulus

34:37

14 6 BIST2 IssuesConclude (*optional)

15:21

12 4 DFT2 Instruction2Conclude

29:24

13 4 BIST1 LFSR polynomial

30:16

14 3 BIST2 Parallel ORA MISR

21:46

12 2 DFT2 JTAG Registers

26:53

11 8 DFT1 IssueSol

36:01

11 7 DFT1 ScanDesignFlow

28:20

11 4 DFT1 Muxed-D Scan ATPG model (*optional)

13:32

11 5 DFT1 ClockScan (*optional)

26:31

9 4 DelayTest PathFsim

26:59

9 3 DelayTest PathTG

34:34

7 8 Combinational ATPG, acceleration techniques

23:35

7 3 Combinational ATPG (Single Path Sensitization)

21:49

2 6 LogicSim Issues (* optional)

26:50

3 5 FaultModeling TransistorFault (* optional)

27:13

3 4 FaultModeling DelayFault

28:16

6 2 Testability SCOAPseq (*optional)

22:00

5 3 FaultSim Deductive

32:11

5 6 FaultSim Alternatives