20:05
Why Artificial ISI for DFE Design & Verification?
20:39
Why Eye Diagram?
13:01
Why Single Pulse Response or Single Shot for ISI Analysis?
13:17
Why Half-Rate or Quarter-Rate RX DFE?
13:49
Why Full-Rate RX DFE?
17:11
Why Half-Rate or Quarter-Rate CDR?
18:37
Why Full-Rate CDR?
13:35
Why Half-Rate or Quarter-Rate Clocking Serializer TX?
12:54
Why Half-Rate Clocking SerDes?
20:17
Why A Multi-Protocol PMA?
15:05
Why Process Evaluation for Transistor, MOSFET Active Device?
17:05
Why Process Evaluation for RLC Passive Elements?
10:04
Why Slope Control CTLE in ADC-DSP PAM4 RX?
13:07
Why Not DFE or Only-1tap Digital DFE in ADC-DSP RX?
19:09
Why ADC/DSP-Based PAM4 Receiver?
17:17
Why Analog PAM4 Receiver?
14:03
Why Dynamic Flip-flops or TSPC FF?
15:30
Why Dynamic Timing Analysis for Setup & Hold Time?
13:29
Why Setup Time & Hold Time Requirements of Latches or Flip-Flops?
12:06
Why Latches or Flip-Flops?
15:03
Why Synchronous or Asynchronous Logic Circuits?
12:20
Why Combinational and Sequential Logic Circuits?
13:15
Why High-Speed Integrating Mode Phase Interpolator, IMPI?
14:43
Why IM PI w/ Inherent 50% Duty Cycle for High-Speed SerDes?
12:41
Why An Integrating Mode Phase Interpolator?
12:36
Why Not A Voltage Mode or A Current Mode Phase Interpolator?
13:06
Why High Linearity Phase Interpolator with Low Power?
16:09
Why IBIS-AMI?
12:10
Why Not IBIS Model Only?
12:16
Why IBIS Model?
14:19
Why Floating Node or High Impedance Node Check?
15:16
Why Dynamic Element Matching, DEM?
13:06
Why Resistor Calibration Circuit, RCC?
20:04
Why Constant Gain or EQ for Robust SI in A Link?
18:09
Why LFEQ?
13:15
Why A On-Chip PVT Sensor for Process / Voltage / Temperature OCV?
10:09
Why Designing Analog Blocks for Local OCV Intuitively & Efficiently?
16:06
Why On-Chip Variation, OCV?
13:02
Why LC VCO Multiphase Clocking for High-speed SerDes?
14:07
Why Negative Skewed or Feed-forward Delay Cell for A Ring-based VCO?
13:03
Why Multiphase VCO for An NRZ or PAM4 ADC or DAC inside the SerDes?
13:08
Why Ring Oscillator Based PLL?
43:04
Why SerDes Design Challenges from Impairments?
14:34
Why Fractional-N PLL?
20:03
为什么 灵活、低功耗和宽范围 的 显示端口 DP 物理介质附件 PMA
20:06
Why a flexible, low-power, and wide-range DisplayPort PMA?
11:03
Why the Design Insights of Charge Pump PLL?
11:30
Why Type 2 PLL instead of Type 1 PLL?
12:46
Why 2D, 2.5D, up to 3D Silicon Stacking and Advanced Packaging Technologies in TSMC 3DFabric™?
14:06
Why Not A Higher Speed SerDes?
11:57
Why A Redriver or A Retimer in A SerDes?
15:30
Why A Low Loss in A SerDes?
10:50
Why Needs A Low Ripple after Chopping Amplifier for A Very Low DC Offset & Flicker Noise?
11:03
Why Design Challenge in Chopping Offset & Flicker Noise?
12:19
Why Dynamic Offset or Mismatch Cancellation with Chopping Technique?
14:21
Why Dynamic Offset or Mismatch Cancellation with Auto-zeroing Technique?
10:29
Why DC Offset Reduction or Mismatch Reduction Techniques through Trimming?
11:37
Why A Periodic Steady-State (PSS), Periodic Noise (Pnoise), and Hand Calculation for A Sampler?
07:01
Why A Low Hysteresis Sampler for A CDR?
10:57
Why Transient Noise (Trannoise) Analysis for A Strong-arm Latch / Comparator?
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