01:42:52

Xilinx DPU End‑to‑End FPGA Deployment (by Mukesh Narayana, PhD Candidate, BITS Goa)

40:46

AM Modulator Part-1

26:03

Ethernet with Standalone

01:22:49

Histogram Equalization IP

09:23

Hardware Software CoDesign with Vivado and Vitis

09:02

Xillinx Vitis Introduction| Hello World with Vitis

15:25

Quartus|Synthesis Part-1|Part-25

17:35

Verilog Implementation of Synchronous Circuits | Quartus | Part24

39:59

Good Coding Style for Embedded Systems |Interrupt Service Routines| Call back functions| Part-2

20:54

LPC2378|Interrupt Controller|Writing ISRs

34:26

FPGA Implementation of Verilog Code|Quartus|Part23

18:41

LPC2378|DAC|Generating Sine wave using microcontroller

13:03

LPC 2378|ADC|Burst Mode

17:18

LPC 2378|ADC|Software Controlled Hardware Triggered mode

28:31

LPC 2378|ADC|Software Controlled Software Triggered mode

48:33

Good Coding Style for Embedded Systems| Part-1

20:17

LPC2378|Timer|MATCH Mode

20:54

LPC2378|Timer|Input capture

16:40

LPC2378|Timer|Free running Counter

33:06

LPC2378|Timer|Free running timer

10:10

LPC2378|GPIO|Interrupts

19:09

LPC2378|GPIO|Enhanced (Fast) Mode

40:39

LPC2378|GPIO|Legacy Mode

39:29

Design of Testbenches Part 2| Reading and Writing from text files| Signal Monitoring Part - 22

42:31

Modelling of Memory Part-3| Modelling Synchronous FIFO|Verilog|Part 26

10:46

Modelling of Memory Part-2| Modelling Read Only Memory (ROM)|Verilog| Part 25

25:19

Modelling of Memory Part-1| Modelling Random Access Memory (RAM)|Verilog| Part 24

18:03

Logic Values| Multiple drive|Verilog|Part 23

40:38

Design of Testbenches Part 1| Generating Clocks| Initial Block| Signal Monitoring Part - 22

21:24

Design of Counters | Part - 21

32:11

Design of a Simple Piano | Declaring Constants in Verilog | Module Parameterization | Part - 20

30:25

Design of Timers | Measurement of Wall clock time | Part - 19

20:23

Design of Encoders and Decoders | Physical implementation of if else if condition | Part 18

16:37

Behavioral Modeling of Combinational Circuits | Latch Inference | Part 17

19:26

Blocking vs Non-blocking Assignment Statements | Part-16

16:35

General Structure of Synchronous Circuits| Behavioral Modeling of Synchronous Circuits| Part-15

17:17

Asynchronous Reset and Preset| Behavioral Modeling| Limitations of Modeling| Part 14

11:57

Behavioral Modeling | Synchronous and Asynchronous Resets | Part 13

20:40

Behavioral Modeling | Modeling a Flip flop | Sequential Circuits | Part 12

28:05

Logical Operators|Implementation of Comparators and Multiplexer|Part 11

25:04

Multiplication, Division and Modulus Operations|Part 10

38:51

Signed and Unsigned Addition in Verilog|System Functions|Part 9

25:38

Assignment, Concatenation and Bitwidth mismatch| Verilog Operators| Part 8

36:34

From Verilog to Chips|Part 7

19:14

Operators in Verilog 1|Bit-wise Operators|Part 6

15:16

Simulation of Adder|ModelSim scripting|Part 5

31:42

Hierarchical Design in Verilog|Instantiations|Verilog|Part 4

22:17

Simulation Basics|Modelsim|Part-3

22:04

First code in Verilog|Module and Port Declarations|Gate Models|Verilog| Part 2

32:28

Introduction to Hardware Description Languages| Verilog HDL | Part 1

24:01

Network on Chip (NoC) with FPGAs|Part 2|Design of a Torus NoC

09:15

Sending email from Lambda Function

14:31

Network on Chip (NoC) with FPGAs|Part 1|Introduction

21:34

Video Interfacing with Zynq (FPGAs): Part 7 Interfacing ZedBoard with HDMI Monitor

16:15

Storing processed data in DynamoDB from AWS Lambda

10:17

Vivado for FPGA design: Part 1 Installation and licensing

05:56

Triggering AWS Lambda from AWS IoT

19:58

What is AWS Lambda? Introduction, Configuration and Testing

15:39

Connecting ZedBoard with Wifi. Controlling Peripherals Programmatically Part 3

20:23

Connecting ZedBoard with Wifi. Controlling Peripherals Part 2