07:05
Blockchain-based Smart Outlet - Demonstrator
25:05
Speculative Temporal Decoupling Using fork()
22:10
25 Years of Turbo Codes: From Mb/s to beyond 100 Gb/s [ISTC18]
34:17
When Channel Coding Hit the Implementation Wall
16:56
Introduction to Blockchain
50:45
Agile FPGA Programming
41:59
Hyper Platform
13:01
Design Space & Terminology
43:49
Creating Custom AXI Master Interfaces Part 4 (Lesson 7)
47:22
Creating Custom AXI Master Interfaces Part 3 (Lesson 7)
53:08
Creating Custom AXI Master Interfaces Part 2 (Lesson 7)
23:10
Creating Custom AXI Master Interfaces Part 1 (Lesson 7)
56:15
Creating Custom AXI Slave Interfaces Part 2 (Lesson 6)
30:51
Creating Custom AXI Slave Interfaces Part 1 (Lesson 6)
01:52:36
AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)
53:37
ZYNQ AXI Interfaces Part 2 (Lesson 4)
39:10
ZYNQ AXI Interfaces Part 1 (Lesson 3)
29:18
ZYNQ Boards (Lesson 2)
33:00
What is ZYNQ? (Lesson 1)
01:31
Thermal Simulation of MPSoCs with Wide-I/O DRAM
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