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Team VLSI @UCVWaC1gXZfHNqwdl6jovsjQ@youtube.com

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Team VLSI Channel demonstrates the flow of EDA tools (like C

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21:18
Derivation for Setup and Hold equations | between +ve and -ve flip flops | Half cycle path | Part-2
35:16
Derivation for Setup and Hold time equations | in Flip Flop | With Numerical example | Part -1
22:27
Common Path Pessimism Removal in VLSI | CPPR in VLSI | CRPR in VLSI
07:41
Signoff order in Physical Design | Various signoff in VLSI | Signoff Checks
16:12
Placement Steps in Physical Design | pre placement and placement steps in VLSI
20:49
Virtual Box + CentOS Installation on window 10 | Download CentOS | Install Linux
09:35
Integrated Clock Gating Cell | ICG Cell in VLSI | Clock Gating Cell | Low Power Techniques in VLSI
16:33
Setup and Hold time inside Latch
21:54
Latch and Flip Flops in ASIC Design
21:30
Setup and Hold Equations S-02 | In Positive and Negative Edge Triggered Flip Flop | Half Cycle Path
40:08
Setup and Hold Timing Equations - S-01| Easy Explanation with Examples | Same types of FF
16:42
Clock Uncertainty in VLSI | Why clock uncertainty | Factors in Clock Uncertainty
09:35
Clock Skew in VLSI | Positive Skew | Negative Skew | Global Skew | Local Skew
12:36
Data and Clock Path | Launch and Capture Flops | Cell delay | Net Delay
09:35
Clock Latency in VLSI | Source Latency | Network Latency | Insertion Delay
17:37
RTL to GDSII flow | Introduction of RTL to GDS Flow | Various EDA tools used in RTL to GDS flow
22:19
Basics of Clock Signal | Characteristics of Clock | Property of Digital Clock
33:26
Reason for Setup and hold time in flip flop | Setup and hold time | clock to q delay | FF using Mux
10:35
False Path in VLSI | Examples of false path | Write false path constraints | Timing exceptions
17:38
Multi cycle path in VLSI | Multi cycle path Constraint | Multi cycle path example
19:56
Temperature Inversion in VLSI | Cell Delay variation with Temperature
04:17
Equations writing in LaTex | Equation copying from another place to LaTex | MathPix snaping tool
02:49
URL Citation in LaTex | How to cite URL /web link in LaTex
25:37
Ecosystem of Semiconductor Industry -II | Overview of VLSI Industries | ASIC Industry in a glance
27:45
Ecosystem of Semiconductor Industry -I | Overview of VLSI Industries | ASIC Industry in a glance
34:00
OCV, AOCV and POCV : a comparative study | difference among OCV, AOCV and POCV | Process Variations
12:52
GDS & OASIS file | Graphical Design System | Need of OASIS over GDSII file | gdsII file | OASIS file
27:16
SPEF file in VLSI | Standard Parasitic Exchange Format file | .spef file in Physical Design
26:28
Filler Cell | Filler Cell in ASIC Design Flow | Layout of Filler Cell
17:04
Tie Cell in ASIC Design | Use of Tie cell | Schematic and Layout of Tie cells | How Tie cells work
16:58
Spare Cell in ASIC Design | Use of Spare Cells | How to add spare cells in design
22:42
Sentaurus TCAD tutorial | Part 2 | MOS Transistor simulation
16:35
DECAP Cell | Use of DeCap Cells | Placement of DeCap Cell | Layout of DeCap Cell
15:52
End Cap or Boundary Cell | Use of endCap Cells | Placement of endCap Cell | Layout of endCap Cell
12:58
Well Tap Cell | Tap Cell | Use of Tap Cells | Placement of Tap Cell | Layout of Tap Cell
34:04
Standard Cell | Standard Cell Layout | Standard Cell Library | Tracks of Standard cells
12:40
Standard Cell Library | Various Cells in Standard Cell Library | Various Files in Standard Cell Lib
33:35
Crosstalk issue and prevention techniques | Crosstalk delay | Shielding of net | part-2
33:33
Crosstalk issue in VLSI | Signal Integrity | crosstalk glitch | crosstalk Noise | part-1
08:08
Semiconductor Device Simulation using TCAD | Sentaurus TCAD | Part-1 | Introductions
29:50
On-Chip Variation in VLSI | OCV | Why OCV occur | How to take care of OCV | AOCV | POCV
21:25
IR Drop issue in VLSI | What is IR drop in ASIC | Why IR Drop | Effects of IR Drop
15:43
Electromigration in VLSI Design | What is electromigration | How to prevent Electromigration
22:55
Antenna Effect Prevention Techniques in VLSI Design
18:19
Antenna effect in VLSI Fabrication | Plasma Induced Gate Oxide Damage | Plasma Etching
27:51
Latch-up prevention in CMOS | Various techniques for latch-up prevention | Issues in Physical design
26:24
Latch-up in CMOS Technology | Latch-up Formation & Triggering | Issues in Physical Design
15:37
Value Change Dump | .vcd file | Switching Activities Interchange Format | .saif file
07:42
TLU Plus file | Milkyway Database | OpenAccess Database | Session-5
28:00
SDC file | Synopsys Design Constraints file | various files in VLSI Design | session-4
32:20
DEF File | Design Exchange Format | Various files in Physical Design | Session -3
23:48
LEF file | Technology file | Description of various files used in VLSI Design | session -2
18:32
LIB file | DB file | Verilog file | Description of various files used in VLSI Design | session-1
26:44
IO pad placement | .io file writing | pad placement in Physical design flow
02:26
Library files format conversion | .lib to .db | .db to .lib | Library Compiler of Synopsys
18:20
Installation Management | Linux System Administration | Part-4
32:35
System Management | Linux System Administration | Part-3
19:10
Network Management in Linux | Linux System Administration | Part-2
34:08
User Management in Linux | Linux System Administration | Part-1
41:58
50 Most Useful Linux Commands | Part-2 | Linux tutorial
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