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Efabless @UCQdKzzTOgO0S1wc3X0Z1Qkg@youtube.com

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efabless.com is the world’s first community engineering plat


27:26
chipIgnite Mini: Prototype Custom ICs on a Mini Budget
42:20
Silicon Showcase - John Kustin - bandgap reference
01:02:16
Extracting secrets from ASICs with Jasper Woudenberg - Audio remaster
25:10
Mastering OpenLane Development Platform in Chip Design
01:00:12
Create the Chip YOU Want: Fast, Tailored ASIC Design with Efabless IP Blocks & Verified Modules
01:01:51
Gaining a better understanding of hardware security by designing your own chips
01:09:50
LLMs for Hardware Design: Tips and techniques
46:53
Introducing PrimisAI's - A Generative AI Tool to Accelerate Hardware Design
57:19
Webinar - Build Your First Chip with Tiny Tapeout
01:05:34
Chipalooza Workshop #3: Physical Verification
02:18
Emilio video
02:05
Hammond video
01:03:52
Layout and Extraction
01:11:42
Webinar - Chipalooza Workshop #1
01:01:23
Webinar - Introduction to chipIgnite
01:01:08
Chipalooza Analog and Mixed-Signal Design Challenge
01:04:44
Webinar - OpenLane Design Integration Options & MPW Chip Bringup
54:38
OpenFrame, GPIO, LVS, Cocotb, IPM, Physical Implementation, OpenLane2 - Webinar, Nov. 30 2023
01:07:56
AI by AI: Neural Network Design - Exploring AI-Driven Hardware
01:01:09
Generative AI for HW Design and Verification
52:41
QuickStart CSAW AI HW Attack Challenge Using chipIgnite
02:13
Silicon Showcase - Matt Venn - Frequency Counter
01:41
Silicon Showcase - Matt Venn - VGA Clock
00:39
AI Generated Open Source Chip Design Contest
21:40
Silicon Showcase - Dinesh Annayya - Riscduino
00:32
Rapid, Affordable, and Custom Chip Design Made Easy with chipIgnite
31:38
webinar AI 6
42:55
AI Generative Workshop: Practical Tips, How to Enter the Contest and Q&A
00:27
Chip design and fabrication for university students and researchers
15:25
Silicon Showcase - Luca Horn - 8 bit MCU on GF180
40:21
Q&A Session on 2nd AI Generated Silicon Design Challenge
01:19:34
AI Generative Workshop: Caravel Overview and Q&A
54:52
Using Generative AI for ASIC Design
09:08
Static Timing Analysis (STA) Quality of Results
01:58
Full Chip STA with Caravel
03:47
Viewing Your Design
02:53
Setting GPIO Defaults
02:22
Setting Up Your Desktop
04:51
Integrating your Design
06:24
Physical Implementation
05:27
RTL Verification
01:42
Demo Design Overview
02:41
Caravel Overview
01:27
Creating an SSH Key
02:47
Submitting Precheck and Tapeout Jobs
01:49
Uploading your Design
02:49
Cloning and Setup
01:16
Creating a Repository
01:13:16
chipIgnite update & AI designed ASIC competition
03:59
AI Generated Design Contest
01:34:53
Analog layout of an op-amp using the Magic VLSI tool
02:19
chipIgnite and OpenMPW Silicon Testing
01:30:10
Analog layout using Magic and Klayout with Tim Edwards and Thomas Parry
02:02
chipIgnite from Efabless - Overview
38:12
How we fixed Caravel - An interview with Andy Wright
01:22:08
Webinar - Analog schematic capture & simulation with Stefan Schippers
00:29
MPW-2 Silicon Testing
07:07
MPW-2 bringup - GPIO characterization
04:31
gf180mcu tutorial part3 xschem issue
03:40
gf180mcu tutorial part4 symbol creation