Prof. Dr. Ben H. Juurlink - PokeTube

Prof. Dr. Ben H. Juurlink @UCPSsA8oxlSBjidJsSPdpjsQ@youtube.com

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The Embedded Systems Architecture (Architektur eingebetteter

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1 1 5 CPU Performance Equation

1 2 2 MIPS64 Addressing Modes and Instruction Formats

1 2 3 MIPS64 Operations

1 3 1 Pipelining Principles

1 3 3 MIPS Pipeline Features and Pipeline Hazards

Test 1 5 1 Caches and the Principle of Locality

Test 1 5 2 Direct mapped Cache Organization

Test 1 5 3 Hit or Miss Example

Test 1 5 4 Basic Cache Optimizations to Reduce Miss Rate

Test 1 5 5 Cache Equations for Set Associative Caches

Test 1 5 6 Cache Metrics and Improving AMAT

Test 1 5 7 Reduce Miss Penalty by Multilevel Cache

Test 1 5 8 Give Priority to Read Misses

Test 2 3 1 Introduction to SIMD

Test 2 3 2 SIMD Register File, Data Types, and Instructions

Test 2 3 3 SIMD Multiplication Instructions

Test 2 3 4 Special Purpose Instructions & Data Conversions

Test 2 3 5 Data Alignment and Reordering

Test 2 3 6 SIMD Control Flow

Test 2 4 1 TLP Motivation and Introduction

Test 2 4 2 SW and HW Multithreading

Test 2 4 3 Introduction to Block Multithreading

Test 2 4 5 Introduction to Interleaved Multithreading

Test 2 4 6 Examples of Interleaved Multithreading

Test 2 4 7 Introduction to Simultaneous Multithreading

Test 2 4 8 Examples of Simultaneous Multithreading

1 3 5 Load use Data Hazard

1 3 8 Scheduling Instructions for Branch Delay Slot

1 3 10 Excercise

1 4 1 Multicycle Operations

1 4 3 MIPS R4000 Pipeline

1 4 4 Code Examples and Pipeline Assumptions

1 4 6 Loop Unrolling

1 4 7 Module Summary

Test 2 3 7 Case Study_Intel SIMD Extensions

Test 2 4 4 Examples of Block Multithreading

1 1 1 Definition And Objectives

1 1 3 Benchmarks

1 1 6 Amdahl's Law

1 5 2 Direct mapped Cache Organization

1 5 4 Basic Cache Optimizations to Reduce Miss Rate

1 5 6 Cache Metrics and Improving AMAT

1 5 7 Reduce Miss Penalty by Multilevel Cache

2 1 1 ILP Concepts and Challenges

1 5 8 Give Priority to Read Misses

2 1 2 Dependences and Hazards

2 1 4 Dynamic Scheduling Using Tomasulo's Algorithm Example

2 1 3 Dynamic Scheduling Using Tomasulo's Algorithm

2 1 5 Extending Tomasulo with Memory Accesses

2 1 7 Introduction to Dynamic Branch Prediction

2 1 8 Advanced Branch Prediction

2 1 9 Tournament Predictors and Branch Prediction Accuracy

2 1 10 Hardware Based Speculation

2 1 11 Multiple Issue

2 1 13 Limitations of ILP

2 2 2 VLIW Challenges Instruction Scheduling & Code Size

2 1 6 Loop Based Dynamic Scheduling Example

2 3 3 SIMD Multiplication Instructions

2 3 4 Special Purpose Instructions & Data Conversions

2 4 6 Examples of Interleaved Multithreading