11:34

VHDL code for Priority Encoder | Part-2/2 | Digital Systems Design | Lec-66

12:46

VHDL code for Priority Encoder | Part-1/2 | Digital Systems Design | Lec-65

12:09

Priority Encoder | Truth Table | Digital Systems Design | Lec-64

12:54

VHDL code for 8x3 Encoder | Digital Systems Design | Lec-63

12:41

8x3 Encoder | Truth table | Digital Systems Design | Lec-62

14:37

VHDL code for Encoder | 4x2 | Data flow model | Digital Systems Design | Lec-61

12:37

Encoder | Introduction | 4x2 | Digital Systems Design | Lec-60

14:44

3 to 8 Decoder | IC 74X138 | VHDL code | Digital Systems Design | Lec-59

12:44

3 to 8 Decoder | two 2 to 4 decoders | Digital Systems Design | Lec-58

13:55

2 to 4 decoder | 74x139 dual | Digital Systems Design | Lec-57

10:47

VHDL code for 3 to 8 Decoder | behavioural | Digital Systems Design | Lec-56

15:02

VHDL code for 3 to 8 Decoder | Data flow | Digital Systems Design | Lec-55

13:43

3 to 8 Decoder | Digital Systems Design | Lec-54

13:30

VHDL code for 2 to 4 Decoder | structural | Digital Systems Design | Lec-53

12:13

VHDL code for Decoder | Dataflow & Behavioural | Digital Systems Design | Lec-52

12:18

Decoder | 2x4 | truth table | Digital Systems Design | Lec-51

20:40

Comparator | 4 bit and 8 bit | Digital Systems Design | Lec-50

14:38

VHDL code for Digital Comparator | 2-bit | Part-2/2 | Digital Systems Design | Lec-49

12:46

Digital Comparator | 2-bit | Part-1/2 | Digital Systems Design | Lec-48

12:34

VHDL code for Demultiplexer | Structural and behavioural | Digital Systems Design | Lec-47

10:41

VHDL code for Demultiplexer | dataflow | Digital Systems Design | Lec-46

12:34

VHDL code for 4X1 multiplexer | dataflow model | Digital Systems Design | Lec-45

14:28

VHDL code Multiplexer | 2x1 4x1 | Dataflow & Behavioral model | Digital Systems Design | Lec-44

13:20

Multiplexer | 4x1, 2x1 | Logic diagram | Digital Systems Design | Lec-43

12:12

VHDL code for BCD Adder | Digital Systems Design | Lec-42

15:16

BCD adder | 4-bit | Circuit design | Digital Systems Design | Lec-41

11:28

If else in verilog | Syntax, Example & Wire statement | Digital Systems Design | Lec-30

14:16

Module statement | Syntax |Types | Digital Systems Design | Lec-29

14:28

VHDL Data Operators | Part-4/4 | Shift & Conditional | Digital Systems Design | Lec-28

12:39

VHDL Data Operators | Part-3/4 | Logical & Relational | Digital Systems Design | Lec-27

12:04

VHDL Data Operators | Part-2/4 | Bitwise & Reduction | Digital Systems Design | Lec-26

15:02

VHDL Data Operators | Part-1/4 | Arithmetic | Digital Systems Design | Lec-25

20:29

VHDL Data types | NET, Register | Digital Systems Design | Lec-24

18:15

Data flow and Behavioral modelling of verilog | Digital Systems Design | Lec-23

12:31

Gate level modeling | Digital Systems Design | Lec-22

12:31

Verilog | Introduction | Digital Systems Design | Lec-21

12:20

Packages in VHDL | Declaration | Digital Systems Design | Lec-20

12:00

VHDL data types I STD LOGIC | Signed & Unsigned | Digital Systems Design | Lec-19

16:53

Carry look ahead adder | VHDL code | Digital Digital Systems Design | Lec - 40

10:23

Carry look ahead adder | Part-2/2 | Digital Systems Design | Lec-39

17:23

Carry look ahead adder | Part-1/2 | Digital Systems Design | Lec-38

12:50

Binary adder and sub tractor | Block Diagram | Digital Systems Design | Lec-37

20:28

Parallel binary adder | RCA | FA | VHDL code |Digital Systems Design | Lec-36

12:34

Parallel binary adder | Block Diagram | Digital Systems Design | Lec-35

11:33

Sub programs | Procedures & Functions | VHDL | Digital Systems Design | Lec-34

12:11

VHDL and Verilog languages | Comparison | Digital Systems Design | Lec-33

12:30

Loop statements | for, while & Loop | Digital Systems Design | Lec-32

13:05

VHDL | Wait, case and Null statement | Digital Systems Design | Lec-31

12:15

designing of synchronous sequential circuits | using state diagram | STLD | Lec-142

12:00

Reduction of state table and state Diagram STLD | Lec-141

17:23

Synchronous sequential circuits | Synthesis | STLD | Lec-140

10:34

Johnson counter | Using D & JK Flip Flops | STLD | Lec-139

09:23

Ring counter | Logic Diagram | Timing Diagram | STLD | Lec-138

15:58

Synchronous counter | Design | JK FlipFlop | STLD | Lec-137

14:38

Asynchronous counters | Mod 6 and Mod 10 | STLD | Lec-136

13:48

Asynchronous counters | Logic & Timing Diagram | STLD | Lec-135

14:06

Counters | Introduction | types | STLD | Lec-134

13:21

Universal shift register | STLD | Lec-133

12:53

Bidirectional shift register | Circuit Diagram | STLD | Lec-132

11:21

Shift register | PISO | PIPO | STLD | Lec-131