23:04

AXI-Stream Arbiter example

05:24

Collaboration with Robert Feranec and new open source SystemVerilog toolbox

29:23

The Critical FPGA Basics: Always blocks, Inferred latches, and why the FPGA needs a clock, anyway?!

15:41

5000 Subscribers! Answering your frequently-asked questions!

07:32

Free FPGA training and resources!

16:12

Zynq Part 3: Combining my own HDL with the Vivado block diagram!

06:01

ILA in a Zynq: View signals in hardware!

20:53

Zynq Part 2: Zynq Vitis Example with PL Fabric GPIO and BRAM

20:00

Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)

23:34

Is chatGPT going to take my job? How well can chatGPT write Verilog?

03:12

AXI Part 3: AXI-Lite testbench (briefly)

08:46

AXI Introduction Part 2: AXI-Lite state machine example explained!

17:40

AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

19:24

Reading from and writing to file: My PDM testbench from start to finish.

05:45

When and how to use the Multiplier IP core

11:19

FPGA Audio to my PC over Ethernet! PDM Microphone and CIC filter explained!

09:30

Handling Ethernet FIFO overflows in SystemVerilog! How to keep packets intact above line rate!

02:40

Receiving packets over Ethernet using Python

02:28

How to use the clocking wizard IP: creating a 50Mhz clock from 100Mhz

20:24

A quick and easy Ethernet Frame state machine, explained from start to finish!

07:37

Digilent Nexys A7-100T Review!

09:05

My Linux + Vivado development environment!

01:21

Bloopers

13:48

Flashing a LED with Vivado and a Nexys A7 FPGA board: Step by step walkthrough!

05:45

Setting up a Nexys board in Linux!

16:11

Polynomial example part 2! Final window code with pipelining!

09:25

Tips for working on a engineering design team as an intern or new graduate!

09:32

Fixing failed timing, a practical example in verilog!

07:12

FPGA unboxing and chat: Why I started this channel and future plans!

13:53

Fixed point basics in Verilog for Beginners! Continuation of polynomial example.

09:08

How do I write to file? Testbench basics for beginners in Verilog!

06:17

Creating input and output delay constraints

07:19

Algorithm preparation for the FPGA: A polynomial window example

08:40

Timing report and RTL schematic interpretation

07:29

Timing Constraints: How do I connect my top level source signals to pins on my FPGA?

12:11

AXI Stream basics for beginners! A Stream FIFO example in Verilog.

10:15

Vivado IP generator tricks: Generating IP, saving to version control, and generating example code!

11:58

10 tips for writing a clear state machine in Verilog: A UART transmitter example.

04:30

What percentage of my always blocks are synchronous?

11:21

How much combinitorial logic is too much? Always block guide for beginners by FPGA professional.

08:51

FPGA Clock and timing concepts explained simply for beginners using two analogies!

04:08

3 PC games that help you practice your FPGA muscles!

04:23

6 Do's and don'ts for good Verilog coding practices

07:52

Generate statement and for loop example in Verilog: A byte-swap in three ways.

20:12

Tips for Verilog beginners from a Professional FPGA Engineer