14:49

Session 6 - 4-bit Adder-cum-subtractor

55:45

Session5 - Blocking vs Non-blocking; Binary-to-BCD

45:09

Session4 - structural modelling and casex example

40:29

Pynq Jupyter

41:04

ILA and VIO @OU

50:37

Session3 - Encoders

01:13:43

Session2 - MUX and Dataflow modelling

01:23:19

Session1 - Intro- Full adder using two half adders

40:04

Exp9 Left_Shift_Register_4bit

40:53

LTSpice Exp4 Half adder

18:06

LTSpice Exp3 NOR gate

27:48

LTSpice Exp2 NAND gate

16:35

LTSpice Exp1 Inverter

18:22

Exp8 up counter

33:23

Exp7 D flipflop

40:07

Exp5 3bit multiplier using Gatelevel modelling[part2 - code]

10:24

Exp5 3bit multiplier using Gatelevel modelling[part1-Theory]

49:59

Exp4 4bit addercumsub using 1bit fa

26:41

Exp3 4bit rca using 1bit fa part2[Code]

15:50

Exp3 4bit rca using 1bit fa part1[Theory]

07:25

Exp2 mux4x1 using mux2x1 - Contd. [with how to display in console]

44:48

Exp2 mux4x1 using mux2x1

32:12

Exp1 fa1bit using 2 ha - contd.

20:29

Exp1 tools and 1bit fa logic

52:02

3 UNIT V ASSOCIATIVE MEMORY PART 3END

41:34

1 UNIT V ASSOCIATIVE MEMORY PART 1

19:03

2 UNIT V ASSOCIATIVE MEMORY PART 2

51:16

9 UNIT IV COA DMA Transfer last topic from DMA and IOP

49:01

8 UNIT IV DMA CONTROLLER PART 2

50:58

7 UNIT IV DMA INTRODUCTION PART 1

52:39

6 UNIT IV INTERRUPT INITIATED IO

50:30

5 UNIT IV Modes of Transfer

42:45

4 UNIT IV TOPIC COVERED ASYNCHRONOUS SERIAL TRANSMISSION

48:19

3 UNIT IV Input output Organization

17:01

2 UNIT IV I O versus Memory Bus

54:29

1 UNIT IV I O Interface I O Bus and Interface Modules

58:29

Session6 - Verilog HDL Behavioral modelling Topic: Encoders [July 20, 2024]

01:18:03

Session5 - Verilog HDL Operators and Behavioral modelling [July 18, 2024]

01:07:08

Session4 - ModelSim GUI mode, Ternary operator and file handler [ July 15, 2024]

01:11:23

Session3 - Structural modelling. [July 13, 2024]

45:41

Session2 - MUX2x1 using gatelevel modelling.[July 10, 2024]

01:26:23

Session1 - Half-adder using gatelevel modelling. [ July 9, 2024]

44:26

OpenLane - without sudo make mount and without docker. [Updated]

25:05

SystemVerilog Array manipulation methods[end] - ordering, reduction methods, Iterator index querying

01:04:07

SystemVerilog Array manipulation methods - Array Locator methods[Index locator]

15:31

SystemVerilog Array manipulation methods - Array Locator methods[end of Element locator] - Part-3

36:03

SystemVerilog array manipulation methods - Array Locator methods[Element locator] : Part-2

42:58

SystemVerilog array manipulation methods - Array locator methods[Element locator] : Part-1

11:21

SystemVerilog Queues - Part-2 [End of the discussion]

13:09

Counter design with SDC file

27:30

SystemVerilog Queues - Part-1

28:33

Associative array in SystemVerilog - Part-3 [End of the discussion]

22:29

Associative array in SystemVerilog - Part-2

20:34

Associative array in SystemVerilog - Part-1 and working of SystemVerilog foreach loop.

14:32

Dynamic Array in SystemVerilog

28:53

System Verilog Data types and Arrays

29:42

Resource sharing - in Digital IC design.

14:36

OpenLane using Codespaces : RTL-to-GDSII flow. - Part-2

53:13

OpenLane using Codespaces : RTL-to-GDSII flow. - Part-1

45:19

Codespaces for Digital IC design [Digital VLSI]