17:01

Optimized Dual Accumulator based RISC Architecture with Advanced Memory and Peripheral Operations

08:28

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications

08:10

A High Speed CRC-32 Implementation on FPGA

06:16

High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing

06:30

Soft-Error-Aware SRAM with Multinode Upset Tolerance for Aerospace Applications

19:15

EFFICIENT IMAGE CONVERSION AND RESTORATION SYSTEM WITH HEXADECIMAL ENCODING AND QUALITY EVALUATION

09:15

Design and Evaluation of Inexact Computation based Systolic Array for Convolution

11:31

Extraction of Fetal ECG from Abdominal and Thorax ECG Using a Non-Causal Adaptive Filter

09:50

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers

05:39

ECG Decompression | A VLSI-Based Hybrid ECG Compression Scheme

07:52

A Reversible Processor Architecture and Its Reversible Logic Design

08:44

Design and Analysis of a Majority Logic Based Imprecise 6-2 Compressor for Approximate Multipliers

09:58

MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier

06:27

Fast and Hardware-Efficient Variable Step Size Adaptive Beamformer

05:31

Design of High Speed 8-bit Vedic Multiplier using Brent Kung Parallel Prefix Adder

06:07

Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient

05:37

An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA

07:48

FPGA Implementation of TFT 1.8 inch SPI 128x160 Display ROM Interface

01:59

VLSI IEEE Projects 2023 | Check Recent 2023 Research Titles

01:25

VLSI Application, Interface and Mini Projects

05:11

FPGA Implementation of Spread Spectrum Clock Generator with Onion Modulation

13:42

An Efficient Image Encryption Algorithm Based on Innovative DES Structure and Hyperchaotic Keys

12:30

An Innovative Area Efficient Pixel Shuffling Method for Image Encryption Algorithm

07:48

FPGA Implementation of 64 Block Data Encryption Standard Algorithm

13:51

FPGA Implementation of Image Line Buffer to Split and reconstruct a 3x3 size of image pixel

11:34

Toward the Multiple Constant Multiplication at Minimal Hardware Cost

10:05

FPGA Implementation of Single Precision Floating Point Multiplier

17:52

Hybrid Protection of Digital FIR Filters

16:14

Smart Intelligent and Adaptive Traffic Controller using FPGA

04:25

MFCC Feature Extraction using MATLAB

25:01

Implementation of High-Precision MFCC Feature Extraction Using FPGA for Speech Recognition

06:21

Design and Implementation of Arithmetic Logic Unit in HDL

09:11

Low power Dadda multiplier using approximate almost full adder

08:38

Efficient Design of Behavioral Clock Divider for Multiple Frequency

11:03

FPGA Heart Rate Monitoring (Pre Processing - QRS Detection Stage)

05:06

Design of Approximate Restoring Divider (8/4 Exact and Approximate Architecture)

06:11

Hamming based Single Fault Error Correction Code

05:12

FPGA Implementation of High Performance Reversible logic based 16x16 Array Multiplier

09:17

FPGA Implementation of 8x8 Truncated Multiplier

12:27

Design of SEU Tolerant 2D-FFT in SRAM-based FPGA

09:22

A Lightweight True Random Number Generator for Root of Trust Applications

06:16

Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process

01:47

IEEE Transactions on VLSI 2023 Research Papers

13:49

Hardware Architecture for Adaptive Edge Directed Interpolation Algorithm

16:45

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters

08:05

A Pipelined Reduced Complexity Two Stages Parallel LMS Structure for Adaptive Beam forming

11:07

Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2

12:29

An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications

18:38

Optimizing Ternary Multiplier Design with Fast Ternary Adder

16:32

A VLSI-Based Hybrid ECG Compression Scheme for Wearable Sensor Node

12:22

AxPPA: Approximate Parallel Prefix Adders

08:14

Design of a Scalable Low Power 1 bit Hybrid Full Adder using Truncated Multiplier

09:56

Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation

11:15

Power Efficient Approximate Divider Architecture for Error Resilient Applications

14:25

Image Demosaicking using Super Resolution Techniques

08:35

Advanced Encryption Standard Algorithm with Optimal S-box and Automated Key Generation

11:35

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error

10:43

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and Wallace

17:47

Reconfigurable Architecture for Real-time Decoding of Canonical Huffman Codes

02:01

NXFEE Innovation Semiconductors IP Design/Development/Services