01:15:42

RISC-V Technical Session | Hardware-Based Detection of Stack Buffer Overflow Attacks on RISC-V

51:48

RISC-V Mentorship Showcase - 2023 Projects

03:46

Interview with Shan Liu of Bejing Institute of Open Source Chip

06:11

Interview with Ron Black, CEO of Codasip

04:25

Interview with Gavin Ferris, CEO of lowRISC

03:10

Interview with Roger Espasa, CEO of Semidynamics

05:13

Interview with Iain Robertson, Siemens EDA

04:02

Interview with Balaji Baktha, CEO of Ventana

09:31

CHERI in out-of-order microarchitecturesFranz Fuchs, University of Cambridge

16:15

The role of an Open Computing Architecture in EU Digital sovereignty - Luis Busquets, DG CONNECT

11:03

Simulate, trace, and evaluate a RISC-V system leveraging very long vectors - Pablo Vizcaino, BSC

10:36

RISC-V enabled, low-power CNN classification in Edge devices - Per Andersson, Lund University

11:09

TETRISC SoC, an fault-tolerant and adaptive quad-core system - Junchao Chen, IHP Microelectronics

08:52

End-to-end flow to automatically generate and integrate RISC-V ISA extensions -Mürmann, TU Darmstadt

10:44

Scale4Edge RISC-V Ecosystem - Andreas Mauderer, Bosch

10:29

RISC-V Instruction Set Explorer (RISE) - Lennart M. Reimann, RWTH Aachen

10:36

The European Accelerator (EPAC) demonstrator with 3 RISC-V based accelerators - F. Mantovanni, BSC

45:30

Hackathon Presentations

13:12

The NOEL Processor LineJan Andersson Nerén, Frontgrade Gaisler

16:12

KVM device assignment for virtual machines using the RISC-V IOMMU - Andrew Jones, Ventana

11:34

Introducing Sonata — the new open source platform for CHERIoT development - Greg Chadwick, lowRISC

11:36

UnityChip Verification: Open-Source RISC-V Verification at BOSC - Shan Liu, BOSC

06:09

ESWIN EIC7700X/7702X, Pioneer of RISC-V Computing Solution - Bo Wang, Beijing ESWIN Computing

11:02

Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips - M. Schleinkofer, Lauterbach

09:09

Exploring RISC-V architectures with VPSim, a virtual prototyping environment - Lilia Zaourar, CEA

02:10

RISC-V Summit Europe 2024

10:29

AI custom Software/Hardware Interface improving performance 5-10x - Keith Graham, Codasip

13:43

Accelerate RISC-V DSA design with Virtual Board Builder - Hualin Wu, Terapines Technology

12:47

Introduction of XuanTie RISC-V - James Shi (Qinghao Shi), Alibaba Damo

10:59

Driving SoC Innovation with Synopsys RISC-V Solutions - Rich Collins, Synopsys

12:23

Andes High Value RISC-V Processors and Their Application - Frankwell Lin, Andes

07:46

Enhancements to SiFive’s Essential product line - Pete Lewin, SiFive

09:03

Breaking the RISC-V Processor Customization Barrier with Formal Verification - Sven Beyer, Siemens

10:52

Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - P Marcuello, Semidynamics

16:49

Unique Program Execution Checking: Formal Security Guarantees for RISC-V Systems - Alex Wezel, RPTU

15:22

Open-source RISC-V Input/Output Physical Memory Protection (IOPMP) IP - Luis Cunha, Uni of Minho

11:26

RISC-V Hypervisor extension formalization in Sail - Lowie Deferme, KU Leuven

09:21

CHERI RISC-V: A Case Study on the CVA6 - Bruno Sa, University of Minho

15:18

Standardizing CHERI for RISC-V - Tariq Kurd, Codasip

16:31

RISC-V and Trusted Electronics: a match made in heaven? - Johanna Baehr, Fraunhofer AISEC

16:33

Open Virtual Platforms APIs Enable High Quality, Easily Maintained RISC-V [..] - Lapides, Synopsys

14:33

VRP: a Variable Precision Accelerator for Scientific Computing Applications - Andrea Bocco, CEA

14:03

Ensuring Datapath Integrity and Adherence with Formal Security Verification [..] - S. Beyer, Siemens

16:58

Instrument Control & Data Processing for high-reliable ‘New Space' [..] - G. Rauwerda, Technolution

03:06

Board of Directors Technical Leadership, Technical Contributor & Software Awards

45:28

RISC-V INNOVATION FORUM

15:28

Bring your code to RISC-V accelerators with SYCL - Charles Macfarlane, Codeplay

15:20

Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis - S. Rokicki, Irisa

13:50

Open-Source Development Platform for RISC-V Application-Specific[..] - K. Hepola, Tampere University

13:09

We had 64-bit, yes. What about second 64-bit? - Mathieu Bacou, Télécom SudParis

15:32

Industry Academia Collaborations on Open Source Hardware Explained - Frank K. Gurkaynak, ETH Zürich

15:42

How to leverage Open Source in Industry - Jean-Roch Coulon, Thales

54:40

RISC-V Technical Session: Digging for Documentation, a Tale of Reverse Engineering

48:09

Panel Discussion "How can Europe engage more in RISC-V?"

31:50

Chips JU and RISC-V - vision, actions, challenges

14:11

Vitamin-V: Expanding Open-Source RISC-V Cloud Environments - Stefano Di Carlo, UPC

16:08

RISC-V@BSC: Fostering RISC-V strategy in the EU through Research, Innovation & Education - T Cervero

10:54

Bringing Tier-1 support for Rust to 64-bit RISC-V Linux - Zivkovic, Codethink Wirth, Ferrous Systems

15:12

Breaking the RISC-V MCUs ecosystem barriers - Giancarlo Parodi, Renesas Electronics

15:36

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications - Rogenmoser, ETHZ