11:24

13. Implementing Division

10:02

12. Implementing Multiplication

10:46

14. Floating-Point Arithmetic

08:09

13-1. Improving the Division Hardware

08:39

12-1. Improving the Multiplication Hardware

05:57

9. Building a 1-bit ALU

07:30

11. Detecting Overflow

01:39

15. Clock Signals

07:08

16. Building Memory Structures

05:29

10. Comparison Operations

03:31

18. Building a D Flip-Flop

03:55

8. Implementing Subtraction

05:02

9-1. Building a 32-bit ALU

11:48

17. Building a D Latch

05:14

7. Building a 1-bit Adder

14:52

7-1. Building a 32-bit Adder

01:49

3. Introduction to Issues in Memory

02:47

3-5. Writing

02:29

3-6. Virtual Memory

02:33

3-3. Associativity

00:55

3-2. Speculation

04:47

1. Introduction to the Memory Hierarchy

03:19

2. Endian-ness

01:21

3-1. Locality

00:19

3-7. Conclusion

01:22

3-4. Replacement

02:11

1-b. Memory Mapped I／O Example 2

02:57

1-a. Memory Mapped I／O Example 1

02:12

1. Introduction to Bus Architecture

00:46

3-2. Synchronous Bus Protocol: Write Timing

02:15

6-1. Bus Arbitration Timing

05:14

5. Asynchronous Bus Protocol

06:33

6. Bus Arbitration

03:11

4. Multi-Cycle Synchronous Bus Protocol

00:43

2. Bus Communication Protocols

01:05

4-1. Multi-Cycle Synchronous Bus Protocol: Realistic Timing

02:46

3-3. Synchronous Bus Protocol: Realistic Read Timing

03:01

3-1. Synchronous Bus Protocol: Read Timing

04:01

4-2. Tomasulo's Algorithm Register Renaming

07:30

4-1-a. Tomasulo's Algorithm Processing Example 1

04:50

2. Static Multiple Issue Processors

02:01

1. Introduction to Instruction Level Parallelism

06:42

4-1-b. Tomasulo's Algorithm Processing Example 2

01:27

3. Dynamic Multiple Issue Processors

02:44

4. Tomasulo's Algorithm

06:55

4-1. Tomasulo's Algorithm Processing

04:54

4-1-c. Tomasulo's Algorithm Processing Example 3

07:23

3-3. Perceptron Branch Predictors

01:34

1. Branch Prediction

02:01

5. Conditional Execution Bits

01:42

3. Dynamic Branch Predictors

07:13

3-1. (m, n) Branch Predictors

05:37

4. Branch Target Buffers

01:44

2. Static Branch Predictors

01:32

3-2. Tournament Branch Predictors

03:32

7-3-b. Forwarding Example 2

03:27

7-3-c. Forwarding Example 3

02:51

8. Control Hazards

03:48

7-3-a. Forwarding Example 1

05:15

7-2-c. Dependencies and Handling Data Hazards Example 3