Munsif M. Ahmad | Poke

Munsif M. Ahmad @UCntxeuZSwvxctHeCTnYIkLw@youtube.com

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Difference between immediate and deferred Immediate assertions w.r.p.t SVA.

Default verbosity level in UVM, Use of get_report_verbosity_level & set_report_verbosity_level.

Handshaking mechanism between sequence and driver

Practical Difference between Mealy and Moore FSM

Mem & register classes declaration w.r.p.t SV UVM RAL.

virtual sequence & virtual sequencer w.r.p.t system Verilog UVM.

RTL code for full-subtractor which is implemented using 2x1 mux.

RTL for Full adder using 2x1 mux.

Simulation and waveform of the RTL with TB code in Questasim.

Schematic View Using Questasim

Types of prediction w.r.p.t SV-UVM RAL

Introduction to SV-UVM RAL(Register Abstraction Layer).

Concept of factory w.r.p.t SV UVM.

Analysis port and export/implementation port w.r.p.t SV-UVM

Reusable covergroup w.r.p.t SV Functional Coverage

Threads w.r.p.t System Verilog.

Mailbox w.r.p.t System Verilog.

Pre and Post randomization in-built methods w.r.p.t system Verilog

logical question on division and modulo operators.

UVM Phases(Build_phase to Final_phase).

set_report_verbosity_level w.r.p.t UVM.

UVM built-in Compare method.

Decoder using using demultiplexer.

this keyword w.r.p.t System Verilog.

How to run C++ code in g++ Ubuntu OS.

Class concept w.r.p.t System Verilog.

Moore FSM Sequence detector overlapping and non-overlapping cases.

Mealy FSM Sequence detector.

FSM for all flip flops.

super.new() in SystemVerilog.

Negedge or falling edge detector using FSM.

Super keyword w.r.p.t System Verilog.

Concept of virtual class w.r.p.t System Verilog.

Verilog code which convert D Flop to SR Flop.

Negedge or falling edge detector.

Posedge or rising edge detector.

Flip flop is a combination of Master & Slave Latches.

Compiler Directives Verilog HDL.

UVM built-in copy method.

Multiplexer using demultiplexer & demultiplexer using multiplexer.

Latch and Flip Flop Difference using Timing diagram.

Inheritance in w.r.p.t System Verilog.

UVM Print Method.

Swapping Using blocking and Non blocking-assignments.

Mux as Universal Logic Simple Trick.

Verilog FAQ Parameter and Parameter Overriding.

K-map easy cell mapping trick !!!

K-map easy cell mapping trick !!!

Full adder and Full subtractor using 2x1 Mux.

Demultiplexer as Universal Logic.

Multiplexer as universal logic.