03:39

IEEE Transactions on VLSI 2022 Research Papers

08:10

A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers

11:26

High Performance Accurate and Approximate Multipliers for FPGA based Hardware Accelerators

08:41

FPGA Implementation of the Adaptive Digital Beamforming for Massive Array

06:57

Approximate Multiplier Design Using Novel Dual-Stage 4 : 2 Compressors

04:38

Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio

12:29

Algorithm Level Error Detection in Low Voltage Systolic Array

09:08

Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy Efficient

07:33

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

12:44

Reconfigurable Digital Delta-Sigma Modulation Transmitter Architecture for Concurrent Multi-Band

05:44

Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability

09:09

Probability-Driven Evaluation of Lower-Part Approximation Adders

11:43

A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder

10:56

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

11:22

Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs

22:54

A Configurable Floating Point Multiple Precision Processing Element for HPC and AI Converged

11:59

Low Cost Online Convolution Checksum Checker

11:22

An Efficient and High Speed Overlap Free Karatsuba Based Finite Field Multiplier

15:57

Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits

12:34

FPGA Implementation of D8PSK Demodulator

13:06

A Low Cost and High Throughtput FPGA Implementation of the Retinex Algorithm

15:16

Reliable CRC Based Error Detection Constructions for Finite Field Multipliers

11:22

FPGA Based High Definition SPWM Generation With Harmonic Mitigation Property

14:36

Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA

08:52

Constant Time Hardware Architecture for a Gaussian Smoothing Filter

06:28

A Three Stage Comparator and Its Modified Version With Fast Speed and Low Kickback

01:49

IEEE Transactions on VLSI 2021 Research Papers

10:15

Floating-point discrete wavelet transform-based image compression on FPGA

07:49

An Efficient Implementation of Floating Point Multiplier

03:42

Design of 7T Sram Cell for Low Power Applications

05:38

A 2.5-V 8-Bit Low power SAR ADC using POLC and SMTCMOS D-FF for IoT Applications

06:09

Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology

13:39

FPGA Implementation of Epileptic Seizure Detection Using ELM Classifier Detection

07:15

ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver

05:11

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled Pull Up Network

13:14

FPGA implementation of low power and high speed image edge detection algorithm

08:47

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial

08:43

A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

15:14

FPGA-Based System For Heart Rate Monitoring

06:56

Low-Cost and Programmable CRC Implementation Based on FPGA

10:34

Design of ultra-low power consumption approximate 4-2 compressors based on the compensation

05:31

A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm

08:18

A Review on Fundamentals of Ternary Reversible Logic Circuits

10:13

High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

09:05

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

07:24

Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration

03:28

Design of a Scalable Low Power 1 bit Hybrid Full Adder for Fast Computation

06:40

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

05:58

An Efficient Design for Reversible Wallace Unsigned Multiplier

09:07

Design and analysis of High speed Wallace tree multiplier using parallel prefix

04:26

Low-Voltage Bandgap Reference Circuit in 28nm CMOS

03:06

A Sub-200nW All-in-One Bandgap Voltage and Current Reference without Amplifiers

14:54

Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector

11:12

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

06:18

Sparse FIR Filter Design via Partial 1-Norm Optimization

05:15

A Compact 0.3 V Class AB Bulk Driven OTA

07:59

Area Delay and Energy Efficient Multi-Operand Binary Tree Adder

04:22

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

08:12

Error Detection and Correction in SRAM Emulated TCAMs

05:25

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications