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Fetch Decode Execute Cycle (Immediate Addressing)
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19,830 Views • Apr 30, 2013 • Click to toggle off description
Describes the fetch decode execute cycle for a machine code instruction that uses immediate addressing
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Views : 19,830
Genre: Education
Date of upload: Apr 30, 2013 ^^


Rating : 4.971 (2/277 LTDR)
RYD date created : 2022-04-06T15:00:10.872228Z
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YouTube Comments - 18 Comments

Top Comments of this video!! :3

@acluster3411

4 months ago

So nicely done!

1 |

@tallsamurai7861

4 years ago

Absolutely stunning work. Thanks for the precise explanations!

1 |

@blochbuster

6 years ago

This is a very nice and clear explanation thank you!

1 |

@johnphilipjones

10 years ago

Thank you for your comment Phil

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@ixi9

5 years ago

brilliant!

1 |

@ibrahimtayyem9260

5 years ago

Thanks a lot :)

1 |

@andrewskyworker

10 years ago

hello can you explain what is buffer register and IR register and why they need it?

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@Noblesse820

9 years ago

one question : so the op code gets from memory via data bus to BR then to IR ,the operand gets from memory via data bus to BR then to register A does the processor know that it has to put the op code to IR and the operand to A ? 

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@mobilealg8367

4 years ago

please, can you tel me how do you know that 3C is icremante A, and 3E is LD A ?. Can you give me the instructios table ? thank you so much!

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@davidfromstow

11 years ago

As always, the canine gonads!

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