Analog & Mixed Signal Design
30 videos • 5,364 views • by Synopsys
1
CoreHW Designing 80-GHz PLL IP using Synopsys Custom Design Family | Synopsys
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2
Design and Verify RFICs – Part 3 | Synopsys
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3
Design and Verify RFICs – Part 2 | Synopsys
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4
Design and Verify RFICs – Part 1 | Synopsys
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5
SRAM Margin Analysis Workflow | Synopsys
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6
Improving Productivity and Ease-of-use of COSIM Setup for Analog-Centric Users | Synopsys
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7
PrimeSim CPU & GPU Technology Delivers Order-of-Magnitude Performance Success I Synopsys
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8
The Latest in Signal and Power Integrity with PrimeSim HSPICE | Synopsys
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9
Faster Analog Design Closure with Early Parasitic Analysis Flow - Part 2 | Synopsys
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10
Faster Analog Design Closure with Early Parasitic Analysis Flow - Part 1 | Synopsys
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11
Demo: 10x Faster Analog Simulation | Synopsys
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12
Accelerating Hyperconvergent IC Design | Synopsys
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13
Accelerate Complex RF Designs using Keysight PathWave ADS Platform Custom Design Platform | Synopsys
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14
Synopsys Custom Design Family | Synopsys
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15
Custom Compiler’s Visually-Assisted Layout Automation in Action – Video Whitepaper | Synopsys
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16
Accelerating Low-Power, High-Speed Data Storage Design using Custom Compiler | Synopsys
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17
Designing for Reliability using Synopsys Custom Design Platform - Overview | Synopsys
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18
Circuit Electrical Rule Checking using Synopsys Custom Design Platform | Synopsys
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19
Analog Fault Simulation using Synopsys Custom Design Platform | Synopsys
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20
Device Aging Analysis using Synopsys Custom Design Platform | Synopsys
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21
Monte Carlo Analysis using Synopsys Custom Design Platform | Synopsys
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22
Effective Design/Layout Collaboration Using Synopsys Custom Design Platform | Synopsys
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23
Accelerating Development of DesignWare Mixed-Signal PHY IP with Custom Compiler | Synopsys
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24
Insights on Extraction for Custom Design & Advanced Nodes | Synopsys
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25
Design of CMOS Image Sensors with Synopsys Custom Design Platform | Synopsys
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26
Accelerate Custom Layout using Custom Compiler’s User-Defined Device (UDD) – Part 2 | Synopsys
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27
Accelerate Custom Layout using Custom Compiler’s User-Defined Device (UDD) | Synopsys
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28
Custom Compiler’s Visually-Assisted Layout Automation in Action | Synopsys
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29
Tackling Analog / RF Simulation Challenges with the Synopsys Custom Design Platform | Synopsys
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30
Introduction to ESP for Custom Design Formal Verification | Synopsys
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