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whyRD @UCgbjHYmRa1l0x0r6lPEdLwg@youtube.com

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48:17
Verilog in Action | Practical Application of FSM to Model Digital Circuits
16:23
NPTEL JULY2024
11:28
One commonly asked Verilog Interview Question | VLSI Puzzle | Solve with me | HDLbits
26:26
My Story: How I Switched from a Software Engineer role to an Electronics Core VLSI job
02:57
#VLSI_Clips: One of the Best way to For ECE BTech VLSI Aspirants
13:17
Best VLSI & AI courses available in NPTEL JANUARY 2024 semester
19:30
8 Action Point to be Market Ready in 2024 | Semiconductor Industry | VLSI |Core Electronics
07:10
These 4 Book is Enough for Best ever 2024 | whyRD
12:56
VLSI Engineers Work Culture | 70 Hours Work Week is Feasible | Time Management
01:39
What is AI ? | Tech Term Simplify | Explained to Any One |
10:06
Best VLSI courses available in NPTEL JANUARY 2024 semester (PART1)
16:50
VLSI Workshop | Robotics Challenge | Multiple Free online Courses for VLSI & AI
18:03
Future of ELECTRONICS Engineers | AI, Neuromorphic & Quantum Computing EXPLAINED as VLSI Engineer
00:58
Must Do for BTech Student #vlsi #shorts
14:06
As an ECE BTech Student, how to be on the VLSI track | VLSI Podcast with whyRD
01:01
Common VLSI Interview Question | How to approach them | VLSI clock domain #1 #shorts #vlsi #whyrd
15:03
Fab-Less or Fab-Lab: Which One is the Best Fit? | whyRD, homes of Electronics Core
18:24
Are Low CGPA Harmful ? College Grade Myths and Winning Strategies | Electronics Core Jobs
17:38
2's Complement | 30 Days of Verilog Coding | Day 30
07:54
Verilog codes from KMap | 30 Days of Verilog Coding | day 29
20:53
Bus Multiplexer Design | 30 days of VERILOG coding | Day 28
20:36
Design controller for Thermostat | Verification | 30 Days of Verilog | Day 27
07:53
Ring or Vibrate | 30 Days of Verilog Coding | Day 26
07:50
Verilog Module Instantiation & Routing | 30 Days of Verilog Coding | Day 25
11:41
Magic of K-Map | 30 Days of Verilog Coding | Day 24
19:47
Digital Design using truth table | Let's Learn Verilog with Real-time Practice with Me | Day 23
27:52
Application of Verilog Generate Block | Lets Learn Verilog with real-time Practice with Me | Day 22
06:19
Count no of 1 | Lets Learn Verilog with real-time Practice with Me | Day 21
16:55
Verilog For loop : can we synthesis it ? Day 20
16:03
Reduction Operator | Lets Learn Verilog with real-time Practice with Me | Day 19
17:36
Simulation vs synthesis | Verilog synthesis using EDA playground | Day 18
17:52
Why casex/casez | Lets Learn Verilog with real-time Practice with Me | Day 17
10:01
What's the need of CASE ? | Lets Learn Verilog with real-time Practice with Me | Day 16
12:15
Danger of Conditional Flow |Lets Learn Verilog with real-time Practice with Me | Day 15
11:20
Conditional Statement | Lets Learn Verilog with real-time Practice with Me | Day 14
29:46
Blocking vs Non-Blocking Assignment | Lets Learn Verilog with real-time Practice with Me | Day 13
17:44
What's the need of Always block ? | Lets Learn Verilog with real-time Practice with Me | Day 12
19:12
Design Full Adder | Lets Learn Verilog with real-time Practice with Me | Day 11
17:00
Design 32bit Adder | Lets Learn Verilog with real-time Practice with Me | Day 10
24:39
Design 4x1 Multiplexer | Lets Learn Verilog with real-time Practice with Me | Day 9
12:40
Design Shift Register| Lets Learn Verilog with real-time Practice with Me | Day 8
14:56
Modules & hierarchy | Lets Learn Verilog with real-time Practice with Me | Day 7
26:46
Lets Learn Verilog with real-time Practice with Me | Vector concatenation | DAY 6
23:27
Lets Learn Verilog with real-time Practice with Me | Bitwise operator vs Logical operator | DAY 5
21:26
Lets Learn Verilog with real-time Practice with Me | Introduction to Vectors | DAY 4
18:55
Lets Learn Verilog with real-time Practice with Me | Codes your first CHIP | Declare wire | DAY 3
07:43
Lets Learn Verilog with real-time Practice with Me | Logic Gates | DAY 2
13:09
Lets Learn Verilog with real-time Practice with Me | A new Beginning | DAY 1
10:00
VLSI Opportunity in India September 2023 | NXP | ISRO | NPTEL | Chips to start-ups | LinkedIN
27:34
Magic VLSI tutorial Day 3| Cmos inverter layout with sky130 PDK
32:45
Magic VLSI tutorial Day 2 | Cmos inverter layout with sky130 PDK
18:17
The Incredible Role of VLSI in Space Exploration | How to Join ISRO | Salary
18:09
IIT vs IISc: Which is Better ? | Students life | Opportunities
29:23
Magic VLSI tutorial | Cmos inverter layout design | Day 1
18:14
How India is Dominating as a Semiconductor maker Despite Not Owning a Single Fab Lab | VLSI Startups
15:45
VLSI Opportunity in India | Internship from IIT | Semicon India | Aug 2023
34:03
Important life lesson | Let me Compensate for your loss | My IKIGAI | 1oh1 with me
12:35
Top 5 Prerequisites for Joining VLSI Training Institutes | Best VLSI scription language | #ASKwhyRD
10:05
This can be the Best Free VLSI resource in NPTEL | NPTEL July Sem |
43:54
VLSI PODCAST : Ditch the Myths: BTech is Enough for VLSI Core Success