02:16

Experiencing glass walk for the first time in Pearl TV Tower, Shanghai. #glasswalk #shanghai

02:56

Beautiful night view of Pearl TV tower located in Shanghai, China. #pearltvtower #shanghai #travel

02:59

Mesmerizing view of water fountain of West lake, Hangzhou, China.

01:46

Trying octopus for the first time in Chinese street.

04:44

Live video of taking pearl out of oyster, in Hangzhou, China.

00:32

Qiantang river, Hangzhou, China. Local call it a mother river.

03:38

Atif Aslam Live Concert in Nepal. Pehli Dafa song.

03:13

Atif Aslam Live Concert in Nepal. Dil Diya Galla song.

04:19

Atif Aslam live concert in Nepal. Tera hune laga hu song.

01:41

Arjit sing live concert in Nepal.

02:02

Arjit Singing Nepali song in concert in Nepal.

11:27

half subtractor in vhdl using vivado

31:16

VHDL introduction and NAND gate using Xilinx Vivado ( Computer architecture lab for CSIT students)

22:45

half adder and full adder in VHDL using Xilinx Vivado

35:12

cache memory organization

38:25

associative memory or content addressable memory(CAM)

23:29

memory organization part 1 ( Memory hierarchy, RAM, ROM Module, mapping of memory

29:37

input output organization part 2 ( interrupt, daisy chain, parallel priority interrupt, DMA, IOP)

56:35

input output organization part 1 ( peripheral devices, polling, interrupt, daisy chain interrupt..)

01:00:37

Digital Logic Revision 4 ( Sequential Circuit part 1)

39:30

Digital Logic Revision 3(Combinational Circuit 2)

27:29

Digital Logic Revision 2 (Combinational circuit 1)

17:01

Digital Logic revision 1 (Number System)

07:21

Digital logic lab part 7(demultiplexer)

09:58

Digital logic lab part 6 (multiplexer 74153IC) class version

05:35

Digital logic lab part 4 (half adder) unedited version

12:31

Digital logic lab part 5 (full adder) unedited version (class version)

13:23

Digital logic lab part 3 (7486 XOR gate)

17:08

Digital logic lab part 2 (7432 IC for OR gate)

05:21

Digital logic lab part 1 introduction(unedited)

01:00:00

microprocessor revision continue (8086, DMA, Interrupt)

51:30

microprocessor revision continue

51:03

microprocessor revision

33:32

ring counter

31:28

4 bit synchrounous up down counter and word time generation

33:45

synchronous counter design

36:40

mod 11 asynchronous counter and introduction to synchronous counter

36:32

mod 10 counter, mod 60 counter and mod 5 counter

36:25

4 bit down counter, frequency divider, application of counter

53:18

division algorithm of signed magnitude number

35:27

counter

34:56

booth algorithm

42:04

signed magnitude multiplication

20:55

application of shift registers and counter introduction

36:08

different types of shift registers

31:02

shift register

24:09

conversion between filip flops

38:42

Design of sequential circuit using various flip-flops

53:37

fixed point computer arithmetic (addition and subtraction algorithm)

45:17

vector processing and matrix multiplication

38:29

sequence detector state diagram

37:43

design of sequential circuit

37:23

sequnce detector

35:33

state reduction, state assignment and excitation table

58:51

arithmetic pipeline and instruction pipeline

35:16

state table, state digaram, mealy and moore model

35:25

analysis of sequential circuit

43:24

space time diagram and speed up factor of pipeline

49:09

pipelining introduction

35:13

different examples on triggering of flip flop