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Education 4u @UCKS34cSMNaXaySe2xgXH-3A@youtube.com

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We are trying to cover all UG courses ( Engineering, BCA, MC


15:15
flip flops | Characteristic equations | STLD | Lec-121
11:55
T Flip flop | The edge triggered | STLD | Lec-120
12:40
J K Flip flop | Edge triggered | STLD | Lec-119
13:29
D flip flop | Edge Triggered | STLD| Lec-118
16:19
S R Flip flop | Edge triggered | Waveforms | STLD | Lec-117
13:12
D Latch | Gated | Truth Table | STLD | Lec-116
18:58
SR latch | Gated | Truth Table | STLD | Lec-115
16:19
S R Latch | NAND gate | STLD | Lec-114
20:17
S R Latch | NOR gate | STLD | Lec-113
13:03
Flip flops | Latches | STLD | Lec-112
18:06
Sequential circuits | Classification | STLD | Lec-111
11:01
PROM | Logic Diagram | Example problem | STLD | Lec-110
21:47
PLA with PLA table | Example problem | STLD | Lec-109
15:34
Design using PLA | STLD | Lec-108
22:39
PAL with PAL table | Example problem | STLD | Lec-107
15:01
Design using PAL | STLD | Lec-106
15:21
Programmable Array Logic | PLA, PROM | STLD | Lec-105
14:59
ROM | Types M-ROM, P-ROM, EPROM, EEPROM | STLD | Lec-104
20:04
ROM | Programmable Logic Device | Part-2/2 | STLD | Lec-103
16:14
Programmable Logic Device | Part-1/2 | STLD | Lec-102
11:01
VHDL and Verilog codes | Differences VHDL & Verilog | Digital Design | Lec-18
16:06
Component declaration and instantiation | VHDL | Digital Design | Lec-17
12:28
Conditional and selected signal assignment statements | VHDL | Digital Design | Lec-16
12:27
Concurrent signal assignment statement | Concurrent Vs Sequential | VHDL | Digital Design | Lec-15
15:07
Process statement | Case, Null , Loop | Part-2/2 | Digital IC Design | Lec-13
17:03
Process statement | Variable, Signal, Wait & If | Part-1/2 | Digital IC Design | Lec-13
15:25
Operators in VHDL | Logical, Relational | Digital IC Design | Lec-12
11:48
Data types | Pre-defined type & Scalar type | Part-2/2 | Digital IC Design | Lec-11
18:35
Data types | Pre-defined type & Scalar type | Part-1/2 | Digital IC Design | Lec-10
11:46
VHDL | Data objects | Signal & File | Part -2/2 | Digital IC Design | Lec-09
13:21
VHDL | Data objects | Constant & Variable | Part -1/2 | Digital IC Design | Lec-08
13:24
VHDL | Identifiers| Basic & Extended | Digital IC Design | Lec-07
16:31
VHDL Code | Configuration and Package declaration | Digital IC Design | Lec-06
22:35
VHDL Structural modeling | Full Adder | Digital IC Design | Lec-05
14:59
VHDL Dataflow modelling | Full Adder | Digital IC Design | Lec-04
10:20
VHDL behavioral modeling | Full Adder | Digital IC Design | Lec-03
16:13
VHDL Architecture | Declaration | Digital IC Design | Lec-02
18:26
Hazards | Static & Dynamic | STLD | Lec-101
21:03
VHDL tutorial for beginners | Entity declaration | Digital IC Design | Lec-01
16:47
2 bit comparator | using two 1 bit comparator modules | STLD | Lec-100
13:37
Demultiplexer | Introduction | 1x4, 1x8 | STLD | Lec-99
16:45
Multiplexer | Boolean logic function | Examples | Part-2/2 | STLD | Lec-97
17:55
Multiplexer | Boolean logic function | Examples | Part-1/2 | STLD | Lec-97
14:42
16x1 multiplexer | using 2 8x1 multiplexers | STLD | Lec-96
13:21
Multiplexer | Introduction | 4x1 Mux | STLD | Lec-95
18:23
BCD to seven segment display | decoder | Logic Diagram | STLD | Lec-94
11:50
Full adder using 3 to 8 decoder | Combinational Logic | STLD | Lec-93
13:25
4 to 16 decoder | using 3 to 8 decoders | STLD | Lec-92
13:28
3 to 8 decoder | Logic Diagram | STLD | Lec-90STLD | Lec-91
16:18
Decoder | 2X4 decoder | Logic Diagram | STLD | Lec-90
13:15
Priority Encoder | Decimal to BCD | Truth Table | STLD | Lec-89
16:43
Priority Encoder | 4 bit | Truth Table | Logic Circuit | STLD | Lec-88
10:28
Decimal to BCD encoder | Truth table | Logic Circuit | STLD | Lec-87
12:03
Encoder | Oct to Binary | Logic Circuit | STLD | Lec-86
13:57
Comparator | IC 7485 | 4-bit | STLD | Lec-85
14:08
2 -bit Comparator | Truth Table | Logic Circuit | STLD | Lec-84
11:22
Comparator | 1-bit | Truth Table | Logic Circuit | STLD | Lec-83
09:07
Odd parity generator | Checker | Circuit | STLD | Lec-82
14:36
Parity generator | checker | Even | STLD | Lec-81
15:25
Code converters | BCD to Binary & Vice Versa | IC's | STLD | Lec-80