Jaya Krishna

05:41

174 || DLD || Counters | Johnson Counter | D Flip Flop | MOD 6 Counter #gate #dld #education

03:45

173 || DLD || Counters | Johnson Counter | Twisted Ring Counter | D Flip Flop #gate #dld

05:36

15:12

13:28

09:17

169 || DLD || Synchronous Counters | consider the following state diagram | flip flops #gate #dld

12:13

168 || DLD || Design a Synchronous Counter | GRAY Counter - T and D Flip flops #gate #dld

11:21

167 || Construction of 2 bit synchronous UP DOWN Counter - T flip flops -Procedure - Circuit Diagram

11:21

166 || Construction of 2 bit synchronous DOWN Counter - JK flip flops -Procedure - Circuit Diagram

05:46

165| Construction of 2 bit synchronous Down Counter using T flip flops - Circuit Diagram - Procedure

08:52

164 || Construction of 2 bit synchronous UP Counter using JK flip flops -Procedure -Circuit Diagram

09:44

163 || Construction of 2 bit synchronous UP Counter using T flip flops - Procedure - Circuit Diagram

11:27

162 || DLD ||Diff. b/w synchronous & asynchronous Counters - SYNC counters & Construction procedure

07:53

161 | DLD | GATE Question on Asynchronous Counters | D Flip Flops | Up and Down Counters #gate #dld

15:59

160 || DLD || MOD 8 Random Counter Using T Flip Flops: State Diagram Explained #gate #dld #tutorial

07:07

159| DLD | Mod 6 Down Counter using JK Flip-Flop | Timing Diagram | Modulo 6 Down Counter #gate #dld

12:47

158 || DLD || Mod 6 Up Counter using JK Flip-Flop | Timing Diagram | Modulo 6 Up Counter #gate #dld

13:27

157 || DLD || 3-Bit Up-Down Counter Using JK Flip-Flops with 2X1 Mux and Basic Gates #gate #dld #jk

04:57

156 || DLD || 2-Bit Positive Edge Up Counter Using JK Flip-Flops: Timing Diagram #dld #gate #jk

24:01

155 || DLD || 3-Bit Asynchronous Up/Down Counter Using JK Flip-Flops: Timings & State Diagram #gate

10:26

154 || DLD || Counters: Synchronous vs. Asynchronous - Circuit Diagrams and Differences Explained

34:17

153| Frequency Division & Counting: 2-Bit Async Up Counters with JK & T Flip-Flops - Timing Diagram

23:28

152 || DLD || Exploring Flip-Flops: Asynchronous JK Flip-Flops vs. Edge-Triggered - Timing Diagrams

07:12

151 || DLD || GATE | Flip Flops | what is the behavior of following one input flipflop x

05:56

150|Conversion of Flip-Flops one to another| XY flip flop using JK| Circuit Diagrams & Truth Tables

16:04

149 || DLD || State Diagrams: Mealy vs. Moore Machines Explained with Examples #gate #dld #tutorial

06:24

148|Conversion of Flip-Flops one to another| X1X2 flip flop using T| Circuit Diagrams & Truth Tables

05:53

147 | Conversion of Flip-Flops one to another | T to JK Flip Flop | Circuit Diagrams & Truth Tables

07:27

146| Conversion of Flip-Flops one to another | JK to T Flip Flop | Circuit Diagrams & Truth Tables

13:01

10:36

10:06

13:35

12:43

139 | DLD || JK Flip Flop - Drawback, Race Around Condition, and Timing Diagram Explained #gate #dld

08:49

138 || DLD || JK Flip Flop: Characteristic Table, Excitation Table, and State Diagram #gate #dld #jk

05:00

137| DLD |JK Flip Flop - Characteristic Table, Minimization & Circuit Diagram Explained #gate #dld

18:20

136 | DLD | JK Flip Flop - NOR Circuit: Characteristic Table and Function Table Explained #gate #dld

22:22

135 || DLD || JK Flip-Flop: NAND Circuit, Characteristic Table, and Function Table #gate #dld #jk

13:55

134 || DLD || JK Flip-Flop: SR Flip-Flop Drawbacks and Circuit Diagrams (Async and Sync) #gate #dld

14:02

133| DLD | SR Flip-Flop Using NAND Gate: Characteristics, Equations, Excitation, and Function Tables

09:16

132 | DLD | SR Flip-Flop Using NOR Gate: Characteristics, Equations, Excitation, and Function Tables

17:04

131 || DLD || Derivation of SR Latch/Flip-Flop Characteristic Table #dld #gate #tutorial #education

08:20

130 || DLD || SR Latch/Flip-Flop: Async and Sync Circuit Representation Using NOR & NAND Gates #gate

08:20

129 || DLD || SR Latch Realization Using NOR and NAND Gates with 4 Types of Clock Signals #gate #dld

01:24

128 || DLD || Exploring Various Types of Latches and Flip-Flops: A Comprehensive Guide #gate #dld

12:13

127 || DLD || Memory Elements in Sequential Circuits: Latch and Flip-Flop Explained #dld #gate

10:45

126 || DLD || Working of Various Types of Clock Signals with Examples (Representations) #gate #dld

06:48

125 || DLD || Understanding Clock Signals: Types and Representations in Digital Circuits #gate #dld

09:20

124 || DLD || Understanding Sequential Circuits: Types and Differences from Combinational Circuits

24:26

123 || DLD || Realizing Combinational Circuits: Using Basic Gates, MUX, and Decoder - Requirements

19:57

122 || DLD || Exploring the IC 74x148: Functionality, Pin Configuration, and Applications #gate #dld

05:00

73 | Collections | Difference between ArrayList and LinkedList | Examples #java #javaplaylist

19:55

121 || DLD || Understanding Logic Levels and Noise Margins in Digital Logic Design #gate #dld

01:27

120 || DLD || Encoders: Understanding the Drawbacks and Limitations #gate #dld #encoder #drawback

08:00

119 || DLD || Understanding Encoders: Exploring Priority Encoders with example #dld #gate #encoder

28:48

118 || DLD || Understanding Encoders and Their Types in Digital Logic Design #gate #dld #tutorial

47:14

01:07:19

117 || DLD || Decoders with Examples #gate #dld #previousyearquestions #tutorial #education

18:54

116 || DLD || Decoder Advantages: ROM Implementation and Address Decoding Explained #dld #gate

59:03

1 | PL/SQL | Difference between SQL and PL/SQL | Basics, Control Structures, Cursors | Execution