02:40

Thyristors

02:07

MOSFETs

02:44

Transistor Amplifiers

03:19

Bipolar Junction Transistors

02:41

Zener Diodes

02:54

Diodes in a Rectifier

02:34

Diodes

01:07

Multisim Circuit Simulation

01:31

Truth Tables and Basic Logic Gates

02:12

Logic Gates Explored and Boolean Algebra

01:53

Binary Conversion and Adders

01:19

Karnaugh Maps

01:58

Encoders and Decoders

02:04

Multiplexers and Demultiplexers

01:26

Comparators

01:46

Latches and Sequential Logic Circuits

03:07

Software Analysis

02:19

ADC and Sampling

02:36

Signal Conditioning

03:41

Sensors and Signals

01:54

Measurements Introduction

04:27

Project Lab - Temperature

01:43

how to install software set add on

02:28

LabVIEW code: Set RT system time/date from PC (walk-through)

02:16

LabVIEW code: Programmatic front-panel communication with RT (walk-through)

04:28

LabVIEW code: "Desktop Execution" node as an FPGA VI testbench (walk-through)

01:15

LabVIEW code: Network-published shared variable (NPSV) (expected results)

00:39

LabVIEW code: Queue (expected results)

00:47

LabVIEW code: Derived clock domains (expected results)

02:39

LabVIEW code: Programmatically access a network-published shared variable (NPSV) (expected results)

01:15

LabVIEW code: Single-process shared variable (SPSV) (expected results)

01:16

LabVIEW code: Set RT system time/date from PC (expected results)

03:27

LabVIEW code: Programmatically access a network-published shared variable (NPSV) (walk-through)

01:22

LabVIEW code: Programmatic front-panel communication with PC (expected results)

03:34

LabVIEW code: Queue (walk-through)

03:07

LabVIEW code: Single-process shared variable (SPSV) (walk-through)

02:18

LabVIEW code: Programmatic front-panel communication with PC (walk-through)

03:53

LabVIEW code: Network-published shared variable (NPSV) (walk-through)

01:49

LabVIEW code: "Desktop Execution" node as an FPGA VI testbench (expected results)

01:19

LabVIEW code: Programmatic front-panel communication with RT (expected results)

02:16

LabVIEW code: Derived clock domains (walk-through)

02:13

LabVIEW code: Augmented default Academic RIO Device FPGA personality (expected results)

02:32

LabVIEW code: Channel wire (walk-through)

03:30

LabVIEW code: Measure loop iteration time (walk-through)

03:51

LabVIEW code: Timer-driven background process using interrupt request (IRQ) (walk-through)

01:00

LabVIEW code: Measure loop iteration time (expected results)

05:49

LabVIEW code: Augmented default Academic RIO Device FPGA personality (walk-through)

01:33

LabVIEW code: Local variable (FPGA) (expected results)

04:54

LabVIEW code: Stream high-speed data between FPGA and RT with a DMA FIFO (expected results)

04:42

LabVIEW code: Externally-triggered action using interrupt request (IRQ) (walk-through)

04:55

LabVIEW code: Stream high-speed data through a network stream channel (walk-through)

05:25

LabVIEW code: Stream high-speed data through a network stream channel (expected results)

06:43

LabVIEW code: Stream high-speed data between FPGA and PC with a DMA FIFO (walk-through)

00:47

LabVIEW code: Local variable (RT) (expected results)

06:10

LabVIEW code: "IP Integration" node for VHDL code reuse (walk-through)

06:57

LabVIEW code: Stream high-speed data between FPGA and RT with a DMA FIFO (walk-through)

02:48

LabVIEW code: Local variable (RT) (walk-through)

03:49

LabVIEW code: Xilinx IP integration (walk-through)

00:57

LabVIEW code: Timer-driven background process using interrupt request (IRQ) (expected results)

03:30

LabVIEW code: Externally-triggered action using interrupt request (IRQ) (expected results)