26:36
Energy Efficiency in Adaptive Neural Circuits
26:07
Memristive Accelerators for Data Intensive Computing
21:07
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing for IoTApplications
25:21
Deep Learning with Coherent Nanophotonic Circuits
21:50
II-V Nanowire TFETs: Performance, Statistics, and Band Edge Sharpness
23:25
Technology Breakthrough by Ferroelectric HfO2 for Ultralow Power Logic and Memory
22:51
Towards Sub-10 nm Diameter InGaAs Vertical nanowire MOSFETs and TFETs
33:13
Prospects for Ultrafast (less than 10 psec) MRAM
02:18
Silicon
01:10
Intro to Electronics: Module 1.1
17:10
4th Berkeley Symposium - Anomalous Properties of Sub-10-nm Magnetic Tunneling Junctions
21:26
4th Berkeley Symposium - Challenges of Fulfilling the Promise of Tunnel FETs
25:58
4th Berkeley Symposium - High-Density 3D Electronic-Photonic Integration
15:32
4th Berkeley Symposium - Photo Detection for Quantum Limit Operation of Optical Links
20:50
4th Berkeley Symposium - A Path Towards Altojoule Photonic Interconnection
29:41
4th Berkeley Symposium - TFET Panel
20:42
4th Berkeley Symposium - Tunneling FET Device Technologies Using III-V and Ge Materials
19:21
4th Berkeley Symposium - A Framework for Generation and Recombination in Tunneling Field
15:16
4th Berkeley Symposium - Prospects for the Low-Voltage TFET: dW/dE vs Dit
42:51
4th Berkeley Symposium - Our computer Systems are not Good Enough
16:17
4th Berkeley Symposium - Understanding Negative Capacitance in Ferroelectric Capacitors
14:35
4th Berkeley Symposium - 2D Tunnel Transistors for Ultra-Low Power Applications
20:23
4th Berkeley Symposium - Influence of interface traps on the performance of Tunnel FETs
29:22
4th Berkeley Symposium - 2D Semiconductor Heterojunctions: van der Waals for Tunnel Transistors
14:33
4th Berkeley Symposium - Body Biased Operation for Improved MEM Relay Energy Efficiency
22:01
4th Berkeley Symposium - Operating Micromechanical Logic Gates Below kBT
25:06
4th Berkeley Symposium - From Microelctromechanical Switches to Nanoelectromechanical Switches
52:11
4th Berkeley Symposium - What the Brain Tells Us About the Future of Silicon
05:35
4th Berkeley Symposium - Keynote Introduction
20:46
4th Berkeley Symposium - Spintronics Panel
14:05
4th Berkeley Symposium - Magnonic Holographic Co-Processor
20:52
4th Berkeley Sumposium - All Spin Logic Device and Circuits
20:13
4th Berkeley Symposium - Electric Field Controlled MRAM
17:07
4th Berkeley Symposium - SOTB Technology Enables Perpetually Reliable CPU for IoT Applications
13:29
4th Berkeley Symposium - Millivolt Switches Will Support Better Engergy-Reliability Tradeoffs
27:01
4th Berkeley Symposium - Superconducting Computing: Lessons from an Emerging Technology
30:13
4th Berkeley Symposium - Specialization for Energy Efficiency by Using Agile Development
05:11
4th Berkeley Symposium - Opening Remarks
27:29
4th Berkeley Symposium - Photonics Panel
02:44
4th Berkeley Symposium - Closing Remarks
03:43
Towards Next Generation Energy Efficient Switches
01:06
32. Closing Remarks
13:28
30. 2.5 GB/s Germanium Gate PhotoMOSFET Integrated to Silicon Photonics
16:42
31. Waveguide-Integrated Optical Antenna nanoLEDs for On-Chip Communication
14:47
29. NEM Relays Using 2-Dimensional Nanomaterials for Low Energy Contacts
26:05
26. The PiezoElectronic Switch: a Path to Low Energy Electronics
25:26
27. Nanoelectromechanical Switching Devices: Scaling Toward Ultimate Energy Efficiency and Longevity
13:46
28. Steep Subthreshold Slope Nanowire Nanoelectromechanical Field-Effect Transistors (NW-NEMFETs)
14:57
25. 2-Dimensional Tunnel Devices and Circuits on Graphene: Opportunities and Challenges
09:31
24. Prospects for High-Aspect-Ratio FinFETs in Low-Power Logic
25:30
20. Operating basic switches toward zero-power computing
14:09
23. Sub-Boltzmann Transistors with Piezoelectric Gate Barriers
28:27
18. Tunnel FETs with Tunneling Aligned with Gate
16:57
21. Full-Quantum Simulation Of Heterojunction TFET Inverters Providing Better Performance
15:58
22. Device Design Considerations for Ultra-Thin Body Non-Hysteretic Negative Capacitance FETs
26:27
17. III-V/Si Heterojunctions for Steep Subthreshold-Slope Transistor
13:23
19. Electrostatic Design of Vertical Tunneling Field-Effect Transistors
44:53
13. FEATURED PRESENTATION - Leveraging Energy & Information Infrastructures
37:24
16. 2D Semiconductors: Contacts, Interfaces, and Heterojunctions
23:37
14. Strained Si Nanowire Tunnel FETs and Inverter
X
About
The Center for Energy Efficient Electronics Science (E3S) is a Science and Technology Center (STC) funded by the National Science Foundation's Integrative Partnerships Program, and is a consortium of world class academic institutions. We are working in a collaborative and innovative environment to make fundamental and conceptual breakthroughs in the underlying physics, chemistry, and materials science of electronic systems, breakthroughs needed to reduce these systems' energy consumption by orders of magnitude.
Tags