Channel Avatar

aldecinc @UCPmeGBznKnLed2QZWwhURWw@youtube.com

2.1K subscribers - no pronouns :c

Aldec, Inc. is an industry-leading EDA company delivering in


09:40
1.7 - Active-HDL™ (v13.1) Basics: Compilation and Simulation
10:15
1.6 - Active-HDL™ (v13.1) Basics: HDL Editor
10:13
1.3 - Active-HDL™ (v13.1) Basics: Library Manager
08:06
1.2 - Active-HDL™ (v13.1) Basics: Design Flow Manager
08:10
1.1 - Active-HDL™ (v13.1) Basics: Workspace
01:01:04
VHDL 2019 Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, & New Environment
20:54
HW/SW Co-simulation solution for Zynq SoC based systems using Riviera-PRO and QEMU
05:07
Riviera PRO Product Overview
18:27
How to Prepare HES DVM Compatible Custom Board Files Using Board Compiler Tool
27:34
How to Automatically Partition an ASIC Design into Multiple FPGAs Using HES DVM
27:33
How to Run User Guided Multi FPGA Partitioning Using Aldec's HES-DVM on the AWS Cloud
18:39
How to Connect Partition's Logical Connections on Multi-FPGA Prototyping Board Using HES-DVM on AWS
13:59
How to Use HES-DVM on the AWS Cloud for Multi-FPGA Design Partitioning and Prototyping
14:06
ALDEC DEMO - HDL Linting for RISC V Cores
35:27
ALDEC DEMO - RISC V Design and Verification with FPGA Hardware In The Loop
26:40
ALDEC DEMO - UVM Based Environment for Ibex RISC V CPU Core with Google RISC V DV
33:50
ALDEC DEMO - Integrated UVM Environment for Verifying Adding Custom Instructions to RISC V Cores
26:03
PCIe 5 Simulation Verification Demonstration
11:42
Unboxing TySOM-3A-ZU19EG Embedded Development Board
19:02
DAC 2019 Demo - Hybrid Co Emulation with ARM Hardware Model
08:54
DAC 2019 Demo - SoC Simulation Environment for Mixed Signal Designs
16:44
DAC 2019 Demo - Partitioning Design for Multi FPGA Prototyping
15:50
DAC 2019 Demo - Register Generator for Design Register Memory Management
03:05
DAC 2019 Demo - DNN Based Object Classification TySOM EDK
09:13
DAC 2019 Demo - Aldec and Silvaco Mixed Signal Simulation
05:02
DAC 2019 Demo - 4K Video Processing Embedded System Design
20:01
DAC 2019 Demo - Advanced UVM Tools in Riviera PRO
03:41
Aldec at Arm TechCon 2018
04:34
Riviera-PRO 1.13 Basics: Alias and Slice Management
06:31
ALINT-PRO™ 3.6 External Tools: Checking Xilinx Vivado Designs in ALINT-PRO
05:43
ALINT-PRO™ 3.5 External Tools: Checking Xilinx ISE Designs in ALINT-PRO
07:18
Static Verification Enhancements in ALINT-PRO
05:24
Generating DO-254 compliant documents for FPGA projects
10:08
What’s New in VHDL 2018 and Open-Source Verification Methodology?
07:54
ALINT-PRO™ 5.1 Methods: Exploration of Finite State Machines
06:01
FPGA-based Implementation of ADAS Bird’s Eye View
07:43
From Traceability to Reusability for Safety-Critical FPGA Projects
05:48
Solving a Sudoku Game with BinCNN
08:15
Why do we need UVM Register Abstraction Layer?
07:58
Simulation Environment for HLS Designs
03:04
Aldec and Silvaco Mixed-Signal Simulation
06:41
Riviera-PRO 2.8 Advanced: UVM Register Generator
04:29
Riviera-PRO 2.7 Advanced: UVM Toolbox
06:00
Aldec at the Embedded Vision 2018
07:44
Riviera-PRO 1.12 Basics: Breakpoint Management
02:54
Riviera-PRO 1.9 Basics: Testbench Creation
05:57
Riviera-PRO 1.5 Basics: Encryption and Security Sharing
07:15
Riviera-PRO 1.8 Basics: Design Profiling
05:23
Riviera-PRO 1.4 Basics: Console in Graphic User Interface
04:55
Riviera-PRO 1.1 Basics: Perspectives and Favorites
05:04
Aldec at DVCon 2018
08:41
ALINT-PRO™ 4.3 Constraints: Chip-Level Design Constraints
06:13
ALINT-PRO™ 3.4 External Tools: Unit Linting in Riviera-PRO
04:32
ALINT-PRO™ 3.2 External Tools: Launching from Riviera-PRO
04:16
ALINT-PRO™ 3.1 External Tools: Launching from Active-HDL
06:22
Riviera-PRO 2.3 Advanced: FSM Coverage & Debug
04:46
Riviera-PRO 5.3 Special Environments: Riviera-PRO and CocoTB
03:57
Riviera-PRO 2.1 Advanced: Code Coverage in HDL Editor
06:08
Riviera-PRO 1.7 Basics: Coverage Overview
06:28
ALINT-PRO™ 3.3 External Tools: Unit Linting in Active-HDL